From 4ec74aebd46c19f776bf3851a05ba8d044906997 Mon Sep 17 00:00:00 2001 From: Jim Wilson Date: Tue, 19 Jan 1993 19:48:11 -0800 Subject: [PATCH] (addsi3): Clean up condition for when to use subo. (umulsidi3): New pattern. (non-canonical nand, nor): Remove paterns. (clrbit, notbit static bit): New patterns. (setbit, clrbit, notbit dynamic bit): New patterns. (setbit static bit non-canonical): Remove pattern. (muldf3, mulsf3, multf3): Add % to operand1. (test recognizers): Use TAB efter mnemonic. From-SVN: r3292 --- gcc/config/i960/i960.md | 88 ++++++++++++++++++++++++++--------------- 1 file changed, 56 insertions(+), 32 deletions(-) diff --git a/gcc/config/i960/i960.md b/gcc/config/i960/i960.md index 5b5bdb65fea..216866a098e 100644 --- a/gcc/config/i960/i960.md +++ b/gcc/config/i960/i960.md @@ -353,14 +353,14 @@ [(set (match_operand:SI 0 "general_operand" "=d") (match_operator 1 "comparison_operator" [(reg:CC 36) (const_int 0)]))] "" - "test%C1 %0" + "test%C1 %0" [(set_attr "type" "compare")]) (define_insn "" [(set (match_operand:SI 0 "general_operand" "=d") (match_operator 1 "comparison_operator" [(reg:CC_UNS 36) (const_int 0)]))] "" - "test%C1 %0" + "test%C1 %0" [(set_attr "type" "compare")]) ;; These control RTL generation for conditional jump insns @@ -1461,8 +1461,7 @@ "" "* { - if (GET_CODE (operands[2]) == CONST_INT - && INTVAL (operands[2]) < 0 && INTVAL (operands[2]) > -32) + if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) return \"subo %n2,%1,%0\"; if (i960_bypass (insn, operands[1], operands[2], 0)) return \"addo %2,%1,%0\"; @@ -1482,6 +1481,19 @@ }" [(set_attr "type" "mult")]) +(define_insn "umulsidi3" + [(set (match_operand:DI 0 "register_operand" "=d") + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) + (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))] + "" + "* +{ + if (i960_bypass (insn, operands[1], operands[2], 0)) + return \"emul %2,%1,%0\"; + return \"emul %1,%2,%0\"; +}" + [(set_attr "type" "mult")]) + ;; This goes after the move/add/sub/mul instructions ;; because those instructions are better when they apply. @@ -1581,40 +1593,64 @@ (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") - (not:SI (and:SI (match_operand:SI 1 "arith_operand" "%dI") - (match_operand:SI 2 "arith_operand" "dI"))))] + (ior:SI (match_operand:SI 1 "arith_operand" "dI") + (match_operand:SI 2 "power2_operand" "n")))] "" "* { - if (i960_bypass (insn, operands[1], operands[2], 0)) - return \"nand %2,%1,%0\"; - return \"nand %1,%2,%0\"; + operands[2] = gen_rtx (CONST_INT, VOIDmode, + bitpos (INTVAL (operands[2]))); + return \"setbit %2,%1,%0\"; }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") - (ior:SI (match_operand:SI 1 "arith_operand" "dI") - (match_operand:SI 2 "power2_operand" "n")))] + (ior:SI (ashift:SI (const_int 1) + (match_operand:SI 1 "register_operand" "d")) + (match_operand:SI 2 "arith_operand" "dI")))] + "" + "setbit %1,%2,%0") + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (and:SI (match_operand:SI 1 "arith_operand" "dI") + (match_operand:SI 2 "cmplpower2_operand" "n")))] "" "* { operands[2] = gen_rtx (CONST_INT, VOIDmode, - bitpos (INTVAL (operands[2]))); - return \"setbit %2,%1,%0\"; + bitpos (~INTVAL (operands[2]))); + return \"clrbit %2,%1,%0\"; }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") - (ior:SI (match_operand:SI 1 "power2_operand" "n") + (and:SI (ashift:SI (const_int 1) + (match_operand:SI 1 "register_operand" "d")) (match_operand:SI 2 "arith_operand" "dI")))] "" + "clrbit %1,%2,%0") + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (xor:SI (match_operand:SI 1 "arith_operand" "dI") + (match_operand:SI 2 "power2_operand" "n")))] + "" "* { - operands[1] = gen_rtx (CONST_INT, VOIDmode, - bitpos (INTVAL (operands[1]))); - return \"setbit %1,%2,%0\"; + operands[2] = gen_rtx (CONST_INT, VOIDmode, + bitpos (INTVAL (operands[2]))); + return \"notbit %2,%1,%0\"; }") +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (xor:SI (ashift:SI (const_int 1) + (match_operand:SI 1 "register_operand" "d")) + (match_operand:SI 2 "arith_operand" "dI")))] + "" + "notbit %1,%2,%0") + (define_insn "iorsi3" [(set (match_operand:SI 0 "register_operand" "=d") (ior:SI (match_operand:SI 1 "arith_operand" "%dI") @@ -1651,18 +1687,6 @@ return \"nor %1,%2,%0\"; }") -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=d") - (not:SI (ior:SI (match_operand:SI 1 "arith_operand" "%dI") - (match_operand:SI 2 "arith_operand" "dI"))))] - "" - "* -{ - if (i960_bypass (insn, operands[1], operands[2], 0)) - return \"nor %2,%1,%0\"; - return \"nor %1,%2,%0\"; -}") - (define_insn "xorsi3" [(set (match_operand:SI 0 "register_operand" "=d") (xor:SI (match_operand:SI 1 "arith_operand" "%dI") @@ -1739,7 +1763,7 @@ (define_insn "muldf3" [(set (match_operand:DF 0 "register_operand" "=d*f") - (mult:DF (match_operand:DF 1 "fp_arith_operand" "rGH") + (mult:DF (match_operand:DF 1 "fp_arith_operand" "%rGH") (match_operand:DF 2 "fp_arith_operand" "rGH")))] "TARGET_NUMERICS" "mulrl %1,%2,%0" @@ -1747,7 +1771,7 @@ (define_insn "mulsf3" [(set (match_operand:SF 0 "register_operand" "=d*f") - (mult:SF (match_operand:SF 1 "fp_arith_operand" "rGH") + (mult:SF (match_operand:SF 1 "fp_arith_operand" "%rGH") (match_operand:SF 2 "fp_arith_operand" "rGH")))] "TARGET_NUMERICS" "mulr %1,%2,%0" @@ -2002,7 +2026,7 @@ (define_insn "multf3" [(set (match_operand:TF 0 "register_operand" "=f") - (mult:TF (match_operand:TF 1 "nonmemory_operand" "fG") + (mult:TF (match_operand:TF 1 "nonmemory_operand" "%fG") (match_operand:TF 2 "nonmemory_operand" "fG")))] "TARGET_NUMERICS" "mulr %1,%2,%0" -- 2.30.2