From 4eca2555b4f27f54924fdc27e6b423b3abf22ce0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 28 Jun 2020 10:23:31 +0100 Subject: [PATCH] merge LDSTPort into TestMemoryPortInterface --- src/soc/experiment/pimem.py | 41 ++----------------------------------- 1 file changed, 2 insertions(+), 39 deletions(-) diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py index 6c3b51d6..ec80b519 100644 --- a/src/soc/experiment/pimem.py +++ b/src/soc/experiment/pimem.py @@ -136,40 +136,6 @@ class PortInterface(RecordObject): ] -class LDSTPort(Elaboratable): - def __init__(self, idx, regwid=64, addrwid=48): - - def elaborate(self, platform): - m = Module() - comb, sync = m.d.comb, m.d.sync - - # latches - # this is a little weird: we let the L0Cache/Buffer set - # the outputs: this module just monitors "state". - - return m - - def connect_port(self, inport): - print ("connect_port", self.pi, inport) - return self.pi.connect_port(inport) - - def __iter__(self): - yield self.pi.is_ld_i - yield self.pi.is_st_i - yield from self.pi.data_len - yield self.pi.busy_o - yield self.pi.go_die_i - yield from self.pi.addr.ports() - yield self.pi.addr_ok_o - yield self.pi.addr_exc_o - - yield from self.pi.ld.ports() - yield from self.pi.st.ports() - - def ports(self): - return list(self) - - class TestMemoryPortInterface(Elaboratable): """TestMemoryPortInterface @@ -189,7 +155,7 @@ class TestMemoryPortInterface(Elaboratable): init=False) self.regwid = regwid self.addrwid = addrwid - self.pi = PortInterface("ldst_port%d" % idx, regwid, addrwid) + self.pi = PortInterface("ldst_port0", regwid, addrwid) @property def addrbits(self): @@ -201,7 +167,7 @@ class TestMemoryPortInterface(Elaboratable): return addr[:self.addrbits], addr[self.addrbits:] def connect_port(self, inport): - return self.lpi.connect_port(inport) + return self.pi.connect_port(inport) def elaborate(self, platform): m = Module() @@ -210,9 +176,6 @@ class TestMemoryPortInterface(Elaboratable): # add TestMemory as submodule m.submodules.mem = self.mem - # connect the ports as modules - m.submodules.port0 = self.lpi - # state-machine latches m.submodules.st_active = st_active = SRLatch(False, name="st_active") m.submodules.ld_active = ld_active = SRLatch(False, name="ld_active") -- 2.30.2