From 4ece8c5a6f1da66d71dc31b25a9ff6fedd0e41c2 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 17 Sep 2022 23:29:42 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls001.mdwn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 04d015f5b..02c620a45 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -246,8 +246,8 @@ count and reducing assembler complexity are: of the predicates provides all of the other types of operations found in Vector ISAs (VEXTRACT, VINSERT etc) again with no need to actually provide explicit such instructions. -* **Saturation**. **all** LD/ST and Arithmetic and Logical operations may - be saturated (without adding explicit saturated opcodes) +* **Saturation**. applies to **all** LD/ST and Arithmetic and Logical + operations (without adding explicit saturation ops) * **Reduction and Prefix-Sum** (Fibonnacci Series) Modes, including a "Reverse Gear" (running loops in reverse order). * **vec2/3/4 "Packing" and "Unpacking"** (similar to VSX `vpack` and `vpkss`) -- 2.30.2