From 4edaa660814b080b688b5c289620c63c99e5a39a Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 5 May 2022 06:08:23 +0100 Subject: [PATCH] --- openpower/sv.mdwn | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn index 6a4e674c6..9717c2080 100644 --- a/openpower/sv.mdwn +++ b/openpower/sv.mdwn @@ -35,10 +35,6 @@ Pages being developed and examples * [[sv/setvl]] the Cray-style "Vector Length" instruction * [[sv/predication]] discussion on predication concepts * [[sv/cr_int_predication]] instructions needed for effective predication -* [[sv/masked_vector_chaining]] -* [[sv/discussion]] -* [[sv/example_dep_matrices]] -* [[sv/major_opcode_allocation]] * [[opcode_regs_deduped]] * [[sv/vector_swizzle]] * [[sv/vector_ops]] @@ -53,8 +49,6 @@ Pages being developed and examples * [[sv/fclass]] detect class of FP numbers * [[sv/int_fp_mv]] Move and convert GPR <-> FPR, needed for !VSX * [[sv/mv.vec]] move to and from vec2/3/4 -* [[sv/16_bit_compressed]] experimental -* [[sv/toc_data_pointer]] experimental * [[sv/ldst]] Load and Store * [[sv/sprs]] SPRs * [[sv/bitmanip]] @@ -64,7 +58,6 @@ Pages being developed and examples * [[sv/propagation]] Context propagation including svp64, swizzle and remap * [[sv/vector_ops]] Vector ops needed to make a "complete" Vector ISA * [[sv/av_opcodes]] scalar opcodes for Audio/Video -* [[sv/byteswap]] * Twin targetted instructions (two registers out, one implicit) Explanation of the rules for twin register targets (implicit RS, FRS) explained in SVP4 [[sv/svp64/appendix]] @@ -72,6 +65,16 @@ Pages being developed and examples - [[isa/svfparith]] * TODO: OpenPOWER [[openpower/transcendentals]] +Examples ideas discussion: + +* [[sv/masked_vector_chaining]] +* [[sv/discussion]] +* [[sv/example_dep_matrices]] +* [[sv/major_opcode_allocation]] +* [[sv/byteswap]] +* [[sv/16_bit_compressed]] experimental +* [[sv/toc_data_pointer]] experimental + Additional links: * -- 2.30.2