From 4efb9d5f7991323c4e5f6f4612072f745399a2f6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 7 Sep 2020 11:58:30 +0100 Subject: [PATCH] whoops truncated the mb and me fields --- src/soc/fu/shift_rot/formal/proof_main_stage.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/fu/shift_rot/formal/proof_main_stage.py b/src/soc/fu/shift_rot/formal/proof_main_stage.py index 05969d31..8e5f9ecd 100644 --- a/src/soc/fu/shift_rot/formal/proof_main_stage.py +++ b/src/soc/fu/shift_rot/formal/proof_main_stage.py @@ -100,9 +100,9 @@ class Driver(Elaboratable): # clear left? with m.If((itype == MicrOp.OP_RLC) | (itype == MicrOp.OP_RLCL)): with m.If(rec.is_32bit): - comb += mb.eq(m_fields.MB[0:-1]) + comb += mb.eq(m_fields.MB) with m.Else(): - comb += mb.eq(md_fields.mb[0:-1]) + comb += mb.eq(md_fields.mb) with m.Else(): with m.If(rec.is_32bit): comb += mb.eq(b[0:6]) @@ -117,9 +117,9 @@ class Driver(Elaboratable): # clear right? with m.If((itype == MicrOp.OP_RLC) | (itype == MicrOp.OP_RLCR)): with m.If(rec.is_32bit): - comb += me.eq(m_fields.ME[0:-1]) + comb += me.eq(m_fields.ME) with m.Else(): - comb += me.eq(md_fields.me[0:-1]) + comb += me.eq(md_fields.me) with m.Else(): with m.If(rec.is_32bit): comb += me.eq(b[0:6]) -- 2.30.2