From 4efc783534320d6a7f7561e76c9a6560456f4fa9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 2 May 2020 11:52:58 +0200 Subject: [PATCH] cpus: add human_name attribute and use it to simplify the BIOS. --- litex/soc/cores/cpu/blackparrot/core.py | 11 ++++++----- litex/soc/cores/cpu/lm32/core.py | 1 + litex/soc/cores/cpu/microwatt/core.py | 1 + litex/soc/cores/cpu/minerva/core.py | 1 + litex/soc/cores/cpu/mor1kx/core.py | 1 + litex/soc/cores/cpu/picorv32/core.py | 1 + litex/soc/cores/cpu/rocket/core.py | 1 + litex/soc/cores/cpu/serv/core.py | 1 + litex/soc/cores/cpu/vexriscv/core.py | 1 + litex/soc/integration/soc.py | 5 +++-- litex/soc/software/bios/main.c | 25 ++++--------------------- 11 files changed, 21 insertions(+), 28 deletions(-) diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py index 6b15a964..03690eb8 100644 --- a/litex/soc/cores/cpu/blackparrot/core.py +++ b/litex/soc/cores/cpu/blackparrot/core.py @@ -47,13 +47,14 @@ GCC_FLAGS = { class BlackParrotRV64(CPU): name = "blackparrot" + human_name = "BlackParrotRV64[ia]" data_width = 64 endianness = "little" gcc_triple = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf") linker_output_format = "elf64-littleriscv" io_regions = {0x50000000: 0x10000000} # origin, length - + @property def mem_map(self): return { @@ -87,10 +88,10 @@ class BlackParrotRV64(CPU): # clock, reset i_clk_i = ClockSignal(), i_reset_i = ResetSignal() | self.reset, - - # irq + + # irq #i_interrupts = self.interrupt, - + #wishbone i_wbm_dat_i = idbus.dat_r, o_wbm_dat_o = idbus.dat_w, @@ -105,7 +106,7 @@ class BlackParrotRV64(CPU): o_wbm_cti_o = idbus.cti, o_wbm_bte_o = idbus.bte, ) - + # add verilog sources self.add_sources(platform, variant) diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py index 42d5a975..f05329fa 100644 --- a/litex/soc/cores/cpu/lm32/core.py +++ b/litex/soc/cores/cpu/lm32/core.py @@ -18,6 +18,7 @@ CPU_VARIANTS = ["minimal", "lite", "standard"] class LM32(CPU): name = "lm32" + human_name = "LM32" data_width = 32 endianness = "big" gcc_triple = "lm32-elf" diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py index ba3867d7..808ac0a7 100644 --- a/litex/soc/cores/cpu/microwatt/core.py +++ b/litex/soc/cores/cpu/microwatt/core.py @@ -16,6 +16,7 @@ CPU_VARIANTS = ["standard"] class Microwatt(CPU): name = "microwatt" + human_name = "Microwatt" data_width = 64 endianness = "little" gcc_triple = ("powerpc64le-linux") diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py index b703f2f1..524cd7f0 100644 --- a/litex/soc/cores/cpu/minerva/core.py +++ b/litex/soc/cores/cpu/minerva/core.py @@ -16,6 +16,7 @@ CPU_VARIANTS = ["standard"] class Minerva(CPU): name = "minerva" + human_name = "Minerva" data_width = 32 endianness = "little" gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed", diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py index 5dea660f..8e91dd94 100644 --- a/litex/soc/cores/cpu/mor1kx/core.py +++ b/litex/soc/cores/cpu/mor1kx/core.py @@ -17,6 +17,7 @@ CPU_VARIANTS = ["standard", "linux"] class MOR1KX(CPU): name = "mor1kx" + human_name = "MOR1KX" data_width = 32 endianness = "big" gcc_triple = "or1k-elf" diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py index ebb96b81..761a926e 100644 --- a/litex/soc/cores/cpu/picorv32/core.py +++ b/litex/soc/cores/cpu/picorv32/core.py @@ -33,6 +33,7 @@ GCC_FLAGS = { class PicoRV32(CPU): name = "picorv32" + human_name = "PicoRV32" data_width = 32 endianness = "little" gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed", diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py index 80d300fe..cac2b05b 100644 --- a/litex/soc/cores/cpu/rocket/core.py +++ b/litex/soc/cores/cpu/rocket/core.py @@ -66,6 +66,7 @@ AXI_DATA_WIDTHS = { class RocketRV64(CPU): name = "rocket" + human_name = "RocketRV64[imac]" data_width = 64 endianness = "little" gcc_triple = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf", diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py index d99661d6..ee31b348 100644 --- a/litex/soc/cores/cpu/serv/core.py +++ b/litex/soc/cores/cpu/serv/core.py @@ -16,6 +16,7 @@ CPU_VARIANTS = ["standard"] class SERV(CPU): name = "serv" + human_name = "SERV" data_width = 32 endianness = "little" gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed", diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index 8e27e5d3..990333bd 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -76,6 +76,7 @@ class VexRiscvTimer(Module, AutoCSR): class VexRiscv(CPU, AutoCSR): name = "vexriscv" + human_name = "VexRiscv" data_width = 32 endianness = "little" gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed", diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 55557ecf..0256fc77 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -793,8 +793,9 @@ class SoC(Module): self.comb += self.cpu.reset.eq(self.ctrl.reset) self.add_config("CPU_RESET_ADDR", reset_address) # Add constants - self.add_config("CPU_TYPE", str(name)) - self.add_config("CPU_VARIANT", str(variant.split('+')[0])) + self.add_config("CPU_TYPE", str(name)) + self.add_config("CPU_VARIANT", str(variant.split('+')[0])) + self.add_constant("CONFIG_CPU_HUMAN_NAME", getattr(self.cpu, "human_name", "Unknown")) def add_timer(self, name="timer0"): self.check_if_exists(name) diff --git a/litex/soc/software/bios/main.c b/litex/soc/software/bios/main.c index e985dd5a..7864260a 100644 --- a/litex/soc/software/bios/main.c +++ b/litex/soc/software/bios/main.c @@ -25,6 +25,7 @@ #include #include +#include #include #include @@ -101,27 +102,9 @@ int main(int i, char **c) printf(" LiteX git sha1: "LITEX_GIT_SHA1"\n"); printf("\n"); printf("--=============== \e[1mSoC\e[0m ==================--\n"); - printf("\e[1mCPU\e[0m: "); -#ifdef __lm32__ - printf("LM32"); -#elif __or1k__ - printf("MOR1KX"); -#elif __picorv32__ - printf("PicoRV32"); -#elif __vexriscv__ - printf("VexRiscv"); -#elif __minerva__ - printf("Minerva"); -#elif __rocket__ - printf("RocketRV64[imac]"); -#elif __blackparrot__ - printf("BlackParrotRV64[ia]"); -#elif __serv__ - printf("SERV"); -#else - printf("Unknown"); -#endif - printf(" @ %dMHz\n", CONFIG_CLOCK_FREQUENCY/1000000); + printf("\e[1mCPU\e[0m: %s @ %dMHz\n", + CONFIG_CPU_HUMAN_NAME, + CONFIG_CLOCK_FREQUENCY/1000000); printf("\e[1mROM\e[0m: %dKB\n", ROM_SIZE/1024); printf("\e[1mSRAM\e[0m: %dKB\n", SRAM_SIZE/1024); #ifdef CONFIG_L2_SIZE -- 2.30.2