From 4eff5b9ed18385a86378c7ae7d0d926a2525f120 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 4 May 2023 11:25:45 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls012.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/rfc/ls012.mdwn b/openpower/sv/rfc/ls012.mdwn index 5e48b6e7b..203be7617 100644 --- a/openpower/sv/rfc/ls012.mdwn +++ b/openpower/sv/rfc/ls012.mdwn @@ -187,7 +187,7 @@ specialist. Found at [[sv/av_opcodes]] these do not require Saturated variants because Saturation is added via [[sv/svp64]] (Vector Prefixing) and -via [[sv/svp64_single]] Scalar Prefixing. This is important to note for +via [[sv/svp64-single]] Scalar Prefixing. This is important to note for Opcode Allocation because placing these operations in the UnVectoriseable areas would irredeemably damage their value. Unlike PackedSIMD ISAs the actual number of AV Opcodes is remarkably small once the usual -- 2.30.2