From 4f1c4147decd8c8b08e2cef2342fa25224cf4225 Mon Sep 17 00:00:00 2001 From: Ayaz Akram Date: Mon, 4 May 2020 21:11:38 -0700 Subject: [PATCH] mem-ruby: Deep renaming of Prefetcher to RubyPrefetcher A recent change (https://gem5-review.googlesource.com/c/ public/gem5/+/27949) updated the ruby prefetcher name, which breaks the use of old name in some SLICC files. This change makes sure that the new name is used at all places. Issue-On: https://gem5.atlassian.net/browse/GEM5-498 Change-Id: Ic667b61eac13dc7c267cee7dce3aa970f7ae9a8b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28667 Reviewed-by: Timothy Hayes Maintainer: Jason Lowe-Power Tested-by: kokoro --- configs/ruby/MESI_Three_Level.py | 2 +- configs/ruby/MESI_Two_Level.py | 2 +- src/mem/ruby/SConscript | 2 +- src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm | 2 +- src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm | 2 +- src/mem/ruby/protocol/RubySlicc_Types.sm | 2 +- .../structures/{Prefetcher.cc => RubyPrefetcher.cc} | 4 ++-- .../structures/{Prefetcher.hh => RubyPrefetcher.hh} | 4 ++-- src/mem/ruby/structures/RubyPrefetcher.py | 10 +++++++--- src/mem/ruby/structures/SConscript | 2 +- src/mem/slicc/symbols/StateMachine.py | 2 +- 11 files changed, 19 insertions(+), 15 deletions(-) rename src/mem/ruby/structures/{Prefetcher.cc => RubyPrefetcher.cc} (99%) rename src/mem/ruby/structures/{Prefetcher.hh => RubyPrefetcher.hh} (99%) diff --git a/configs/ruby/MESI_Three_Level.py b/configs/ruby/MESI_Three_Level.py index 61d6c523b..0bd893e38 100644 --- a/configs/ruby/MESI_Three_Level.py +++ b/configs/ruby/MESI_Three_Level.py @@ -121,7 +121,7 @@ def create_system(options, full_system, system, dma_ports, bootmem, clk_domain = system.cpu[i].clk_domain # Ruby prefetcher - prefetcher = RubyPrefetcher.Prefetcher( + prefetcher = RubyPrefetcher( num_streams=16, unit_filter = 256, nonunit_filter = 256, diff --git a/configs/ruby/MESI_Two_Level.py b/configs/ruby/MESI_Two_Level.py index 8d2e01fb6..3ddf8eff7 100644 --- a/configs/ruby/MESI_Two_Level.py +++ b/configs/ruby/MESI_Two_Level.py @@ -78,7 +78,7 @@ def create_system(options, full_system, system, dma_ports, bootmem, start_index_bit = block_size_bits, is_icache = False) - prefetcher = RubyPrefetcher.Prefetcher() + prefetcher = RubyPrefetcher() # the ruby random tester reuses num_cpus to specify the # number of cpu ports connected to the tester object, which diff --git a/src/mem/ruby/SConscript b/src/mem/ruby/SConscript index 8c22ae495..fc90f8a62 100644 --- a/src/mem/ruby/SConscript +++ b/src/mem/ruby/SConscript @@ -126,7 +126,7 @@ MakeInclude('structures/CacheMemory.hh') MakeInclude('structures/DirectoryMemory.hh') MakeInclude('structures/PerfectCacheMemory.hh') MakeInclude('structures/PersistentTable.hh') -MakeInclude('structures/Prefetcher.hh') +MakeInclude('structures/RubyPrefetcher.hh') MakeInclude('structures/TBETable.hh') MakeInclude('structures/TimerTable.hh') MakeInclude('structures/WireBuffer.hh') diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm index 3639ef2c5..4de4a293e 100644 --- a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm +++ b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm @@ -46,7 +46,7 @@ machine(MachineType:L0Cache, "MESI Directory L0 Cache") Cycles response_latency := 2; bool send_evictions; - Prefetcher * prefetcher; + RubyPrefetcher * prefetcher; bool enable_prefetch := "False"; // From this node's L0 cache to the network diff --git a/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm b/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm index 7c83478db..3e3580f70 100644 --- a/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm +++ b/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm @@ -30,7 +30,7 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP") : Sequencer * sequencer; CacheMemory * L1Icache; CacheMemory * L1Dcache; - Prefetcher * prefetcher; + RubyPrefetcher * prefetcher; int l2_select_num_bits; Cycles l1_request_latency := 2; Cycles l1_response_latency := 2; diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm b/src/mem/ruby/protocol/RubySlicc_Types.sm index 66d84fca3..6ab0f3f76 100644 --- a/src/mem/ruby/protocol/RubySlicc_Types.sm +++ b/src/mem/ruby/protocol/RubySlicc_Types.sm @@ -246,7 +246,7 @@ structure (TimerTable, inport="yes", external = "yes") { bool isSet(Addr); } -structure (Prefetcher, external = "yes") { +structure (RubyPrefetcher, external = "yes") { void observeMiss(Addr, RubyRequestType); void observePfHit(Addr); void observePfMiss(Addr); diff --git a/src/mem/ruby/structures/Prefetcher.cc b/src/mem/ruby/structures/RubyPrefetcher.cc similarity index 99% rename from src/mem/ruby/structures/Prefetcher.cc rename to src/mem/ruby/structures/RubyPrefetcher.cc index 06021159c..8646b9932 100644 --- a/src/mem/ruby/structures/Prefetcher.cc +++ b/src/mem/ruby/structures/RubyPrefetcher.cc @@ -38,7 +38,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "mem/ruby/structures/Prefetcher.hh" +#include "mem/ruby/structures/RubyPrefetcher.hh" #include "base/bitfield.hh" #include "debug/RubyPrefetcher.hh" @@ -46,7 +46,7 @@ #include "mem/ruby/system/RubySystem.hh" RubyPrefetcher* -PrefetcherParams::create() +RubyPrefetcherParams::create() { return new RubyPrefetcher(this); } diff --git a/src/mem/ruby/structures/Prefetcher.hh b/src/mem/ruby/structures/RubyPrefetcher.hh similarity index 99% rename from src/mem/ruby/structures/Prefetcher.hh rename to src/mem/ruby/structures/RubyPrefetcher.hh index 4d2513f78..b691d3d86 100644 --- a/src/mem/ruby/structures/Prefetcher.hh +++ b/src/mem/ruby/structures/RubyPrefetcher.hh @@ -51,7 +51,7 @@ #include "mem/ruby/slicc_interface/AbstractController.hh" #include "mem/ruby/slicc_interface/RubyRequest.hh" #include "mem/ruby/system/RubySystem.hh" -#include "params/Prefetcher.hh" +#include "params/RubyPrefetcher.hh" #include "sim/sim_object.hh" #include "sim/system.hh" @@ -93,7 +93,7 @@ class PrefetchEntry class RubyPrefetcher : public SimObject { public: - typedef PrefetcherParams Params; + typedef RubyPrefetcherParams Params; RubyPrefetcher(const Params *p); ~RubyPrefetcher(); diff --git a/src/mem/ruby/structures/RubyPrefetcher.py b/src/mem/ruby/structures/RubyPrefetcher.py index d762ba530..38397c334 100644 --- a/src/mem/ruby/structures/RubyPrefetcher.py +++ b/src/mem/ruby/structures/RubyPrefetcher.py @@ -42,10 +42,10 @@ from m5.proxy import * from m5.objects.System import System -class Prefetcher(SimObject): - type = 'Prefetcher' +class RubyPrefetcher(SimObject): + type = 'RubyPrefetcher' cxx_class = 'RubyPrefetcher' - cxx_header = "mem/ruby/structures/Prefetcher.hh" + cxx_header = "mem/ruby/structures/RubyPrefetcher.hh" num_streams = Param.UInt32(4, "Number of prefetch streams to be allocated") @@ -58,3 +58,7 @@ class Prefetcher(SimObject): cross_page = Param.Bool(False, """True if prefetched address can be on a page different from the observed address""") sys = Param.System(Parent.any, "System this prefetcher belongs to") + +class Prefetcher(RubyPrefetcher): + """DEPRECATED""" + pass diff --git a/src/mem/ruby/structures/SConscript b/src/mem/ruby/structures/SConscript index 9e2bde924..0cf05598f 100644 --- a/src/mem/ruby/structures/SConscript +++ b/src/mem/ruby/structures/SConscript @@ -40,6 +40,6 @@ Source('DirectoryMemory.cc') Source('CacheMemory.cc') Source('WireBuffer.cc') Source('PersistentTable.cc') -Source('Prefetcher.cc') +Source('RubyPrefetcher.cc') Source('TimerTable.cc') Source('BankedArray.cc') diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py index 0904ac63f..1263344aa 100644 --- a/src/mem/slicc/symbols/StateMachine.py +++ b/src/mem/slicc/symbols/StateMachine.py @@ -61,7 +61,7 @@ python_class_map = { "MemoryControl": "MemoryControl", "MessageBuffer": "MessageBuffer", "DMASequencer": "DMASequencer", - "Prefetcher":"Prefetcher", + "RubyPrefetcher":"RubyPrefetcher", "Cycles":"Cycles", } -- 2.30.2