From 4f4e70876f06738fa7dda24e01ac296fe318264a Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Thu, 18 Mar 2021 13:38:25 -0400
Subject: [PATCH] sv: allow typenames as function return types

---
 frontends/verilog/verilog_parser.y |  6 +++++
 tests/verilog/func_typename_ret.sv | 35 ++++++++++++++++++++++++++++++
 tests/verilog/func_typename_ret.ys |  5 +++++
 3 files changed, 46 insertions(+)
 create mode 100644 tests/verilog/func_typename_ret.sv
 create mode 100644 tests/verilog/func_typename_ret.ys

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index ea8cc0765..91b7afddf 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -861,6 +861,7 @@ task_func_decl:
 			outreg->children.push_back($4);
 			outreg->is_signed = $4->is_signed;
 			$4->is_signed = false;
+			outreg->is_custom_type = $4->type == AST_WIRETYPE;
 		}
 		current_function_or_task->children.push_back(outreg);
 		current_function_or_task_port_id = 1;
@@ -871,6 +872,11 @@ task_func_decl:
 	};
 
 func_return_type:
+	hierarchical_type_id {
+		$$ = new AstNode(AST_WIRETYPE);
+		$$->str = *$1;
+		delete $1;
+	} |
 	opt_type_vec opt_signedness_default_unsigned {
 		$$ = makeRange(0, 0, $2);
 	} |
diff --git a/tests/verilog/func_typename_ret.sv b/tests/verilog/func_typename_ret.sv
new file mode 100644
index 000000000..423975f97
--- /dev/null
+++ b/tests/verilog/func_typename_ret.sv
@@ -0,0 +1,35 @@
+typedef logic [1:0] T;
+
+package P;
+    typedef logic [3:0] S;
+endpackage
+
+module gate(
+    output wire [31:0] out1, out2
+);
+    function automatic T func1;
+        input reg signed inp;
+        func1 = inp;
+    endfunction
+    assign out1 = func1(1);
+    function automatic P::S func2;
+        input reg signed inp;
+        func2 = inp;
+    endfunction
+    assign out2 = func2(1);
+endmodule
+
+module gold(
+    output wire [31:0] out1, out2
+);
+    function automatic [1:0] func1;
+        input reg signed inp;
+        func1 = inp;
+    endfunction
+    assign out1 = func1(1);
+    function automatic [3:0] func2;
+        input reg signed inp;
+        func2 = inp;
+    endfunction
+    assign out2 = func2(1);
+endmodule
diff --git a/tests/verilog/func_typename_ret.ys b/tests/verilog/func_typename_ret.ys
new file mode 100644
index 000000000..7f6049961
--- /dev/null
+++ b/tests/verilog/func_typename_ret.ys
@@ -0,0 +1,5 @@
+read_verilog -sv func_typename_ret.sv
+proc
+equiv_make gold gate equiv
+equiv_simple
+equiv_status -assert
-- 
2.30.2