From 4f6b8f1d7108e0af786bbcbac24487b5e05c0cd1 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 20 Mar 2020 19:41:29 +0000 Subject: [PATCH] dev-arm: Fix pci_mem_base setting in VExpress_GEM5_Base This was not actually used and DTB was generated using an hardcoded value. Change-Id: Ie8fd63495df5cb56418593cf0dd5432dc2992eac Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27288 Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com> Reviewed-by: Nikos Nikoleris Maintainer: Nikos Nikoleris --- src/dev/arm/RealView.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index 43d2b1553..cf57ee208 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -160,7 +160,7 @@ class GenericArmPciHost(GenericPciHost): # AXI memory address range ranges += self.pciFdtAddr(space=2, addr=0) - ranges += state.addrCells(0x40000000) # Fixed offset + ranges += state.addrCells(self.pci_mem_base) ranges += local_state.sizeCells(0x40000000) # Fixed size node.append(FdtPropertyWords("ranges", ranges)) @@ -1025,6 +1025,7 @@ Interrupts: pci_host = GenericArmPciHost( conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, pci_pio_base=0x2f000000, + pci_mem_base=0x40000000, int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4) energy_ctrl = EnergyCtrl(pio_addr=0x10000000) -- 2.30.2