From 4f9d4560e6db256d801e0e23d66821367705fb9a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 29 Jun 2019 22:05:53 +0100 Subject: [PATCH] whitespace --- simple_v_extension/vblock_format.mdwn | 22 +++++++++++++-------- simple_v_extension/vblock_format_table.mdwn | 14 ++++++------- 2 files changed, 21 insertions(+), 15 deletions(-) diff --git a/simple_v_extension/vblock_format.mdwn b/simple_v_extension/vblock_format.mdwn index 669bcce9f..49b005cbe 100644 --- a/simple_v_extension/vblock_format.mdwn +++ b/simple_v_extension/vblock_format.mdwn @@ -27,21 +27,27 @@ as follows: Note: The VL Block format is similar to that used in [[sv_prefix_proposal]]. -* Mode 0b00: set VL to the immediate, truncated to not exceed MVL. Register rd is also set to the same value, if not x0. -* Mode 0b01: follow [[sv.setvl]] rules except with RVC style registers in the range x8-x15 for rs1 and rd. -* Mode 0b10: set both MVL and VL to the immediate. Register rd is also set if not x0. +* Mode 0b00: set VL to the immediate, truncated to not exceed + MVL. Register rd is also set to the same value, if not x0. +* Mode 0b01: follow [[sv.setvl]] rules except with RVC style registers + in the range x8-x15 for rs1 and rd. +* Mode 0b10: set both MVL and VL to the immediate. Register rd is also + set if not x0. * Mode 0b11: reserved. All fields must be zero. Mode 0b01 will typically be used to start vectorised loops, where the VBLOCK instruction effectively embeds an optional "SETSUBVL, SETVL" sequence (in compact form). -Modes 0b00 and 0b10 will typically not be used so much for loops as they will be -for one-off instructions such as saving the entire register file to the -stack with a single one-off Vectorised and predicated LD/ST, or as a way -to save or restore registers in a function call with a single instruction. +Modes 0b00 and 0b10 will typically not be used so much for loops as they +will be for one-off instructions such as saving the entire register file +to the stack with a single one-off Vectorised and predicated LD/ST, +or as a way to save or restore registers in a function call with a +single instruction. -Unlike in RVV, VL is set (within the limits of MVL) to exactly the value requested, specifically so that LD/ST-MULTI style behaviour can be done in a single instruction. +Unlike in RVV, VL is set (within the limits of MVL) to exactly the value +requested, specifically so that LD/ST-MULTI style behaviour can be done +in a single instruction. # VBLOCK Prefix diff --git a/simple_v_extension/vblock_format_table.mdwn b/simple_v_extension/vblock_format_table.mdwn index c28a5ef98..ca3ef5176 100644 --- a/simple_v_extension/vblock_format_table.mdwn +++ b/simple_v_extension/vblock_format_table.mdwn @@ -14,12 +14,12 @@ of the RISC-V ISA, is as follows: The VL/MAXVL/SubVL Block format: [[!table data=""" -31:30 | 29:28 | 27:22 | 21 | 20:19 | 18:16 | comment | -0b00 | SubVL |imm[5:0]|rsvd| 00000 || VL = MIN(MVL, imm) | -0b00 | SubVL |imm[5:0]|rsvd| rd[4:0] || rf[rd] = VL = MIN(MVL, imm) | -0b01 | SubVL |imm[5:0]| rs1[2:0] || rd[2:0] | RVC reg format, sv.setvl rd, rs, imm | -0b10 | SubVL |imm[5:0]|rsvd| 00000 || VL = MVL imm | -0b10 | SubVL |imm[5:0]|rsvd| rd[4:0] || rf[rd] = VL = MVL imm | -0b11 | rsvd | rsvd |rsvd| rsvd || reserved, all 0s | +31:30 | 29:28 | 27:22 | 21 | 20:19 | 18:16 | comment | +0b00 | SubVL | imm[5:0] |rsvd| 00000 || VL = MIN(MVL, imm) | +0b00 | SubVL | imm[5:0] |rsvd| rd[4:0] || rf[rd] = VL = MIN(MVL, imm) | +0b01 | SubVL | imm[5:0] | rs1[2:0] || rd[2:0] | RVC reg format, sv.setvl rd, rs, imm | +0b10 | SubVL | imm[5:0] |rsvd| 00000 || VL = MVL imm | +0b10 | SubVL | imm[5:0] |rsvd| rd[4:0] || rf[rd] = VL = MVL imm | +0b11 | rsvd | rsvd |rsvd| rsvd || reserved, all 0s | """]] -- 2.30.2