From 4fac5ab8155acbb3964a15ce5e238cfa12dea0c7 Mon Sep 17 00:00:00 2001 From: lkcl Date: Tue, 13 Sep 2022 15:45:58 +0100 Subject: [PATCH] --- openpower/sv/svp64.mdwn | 2 ++ 1 file changed, 2 insertions(+) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index d742556c6..b1f672599 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -40,6 +40,8 @@ Table of contents # Introduction This document focuses on the encoding of [[SV|sv]], and assumes familiarity with the same. It does not cover how SV works (merely the instruction encoding), and is therefore best read in conjunction with the [[sv/overview]], as well as the [[sv/svp64_quirks]] section. +It is also crucial to note that whilst this format augments instruction +behaviour it works in conjunction with SVSTATE and other [[sv/sprs]]. All bit numbers are in MSB0 form (the bits are numbered from 0 at the MSB and counting up as you move to the LSB end). All bit ranges are inclusive -- 2.30.2