From 4fbbf63bf780b31c3e25b7e3c1177da9a5ebc518 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 16 Sep 2022 12:33:42 +0100 Subject: [PATCH] clarify --- openpower/sv/rfc/ls001.mdwn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index be389e575..d4cf3eb17 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -247,9 +247,9 @@ count and reducing assembler complexity are: found in Vector ISAs (VEXTRACT, VINSERT etc) again with no need to actually provide explicit such instructions. * **Saturation**. **all** LD/ST and Arithmetic and Logical operations may - be saturated (without adding explicit scalar saturated opcodes) + be saturated (without adding explicit saturated opcodes) * **Reduction and Prefix-Sum** (Fibonnacci Series) Modes, including a - "Reverse Gear". + "Reverse Gear" (running loops in reverse order). * **vec2/3/4 "Packing" and "Unpacking"** (similar to VSX `vpack` and `vpkss`) accessible in a way that is easier than REMAP, added for the same reasons that drove `vpack` and `vpkss` etc. to be added: pixel, audio, and 3D -- 2.30.2