From 4fbe877ad4c40dfb0f9d2fb3610983085ce13f71 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 3 Nov 2020 13:50:32 +0000
Subject: [PATCH] format table

---
 HDL_workflow/ECP5_FPGA.mdwn | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index 83d1c6ab1..e4d7f8235 100644
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -165,9 +165,9 @@ Additionally, does the note in the schematic about needing to swap EVEN and ODD
 
 # VERSA ECP5 Connections
 
-|-------------|-------------|----------------|-----------|
-|             |             |STLINKV2  JTAG  |           |
-|    pin #    | FPGA IO PAD | Pin #  (Signal)|Wire Colour|
+Table of connections:
+
+| X3  pin #   | FPGA IO PAD | STLinkv2       |Wire Colour|
 |-------------|-------------|----------------|-----------|
 |1 GND        | GND         | GND            |   Black   |
 |2 NC         |NOT CONNECTED| NOT CONNECTED  |    NC     |
-- 
2.30.2