From 4fcb52c4ef09d1b0f9f7afeb60ccf040cfaa1262 Mon Sep 17 00:00:00 2001 From: Tamar Christina Date: Thu, 7 Feb 2019 10:05:57 +0000 Subject: [PATCH] Arm: Fix NEON REG to REG reload failures. (PR/target 88850) We currently return cost 2 for NEON REG to REG moves, which would be incorrect for 64 bit moves. We currently don't have a pattern for this in the neon_move alternatives because this is a bit of a special case. We would almost never want it to use this r -> r pattern unless it really has no choice. As such we add a new neon r -> r move pattern but also hide it from being used to determine register preferences and also disparage it during LRA. gcc/ChangeLog: PR/target 88850 * config/arm/neon.md (*neon_mov): Add r -> r case. gcc/testsuite/ChangeLog: PR/target 88850 * gcc.target/arm/pr88850.c: New test. From-SVN: r268612 --- gcc/ChangeLog | 5 +++++ gcc/config/arm/neon.md | 15 ++++++++------- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/arm/pr88850.c | 22 ++++++++++++++++++++++ 4 files changed, 40 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/pr88850.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index eabd7c9edc4..3ac46690dda 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2019-02-07 Tamar Christina + + PR/target 88850 + * config/arm/neon.md (*neon_mov): Add r -> r case. + 2019-02-07 Kyrylo Tkachov * config/arm/neon.md (neon_dot): diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 4a2c7b99881..de9ae438490 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -25,9 +25,9 @@ (define_insn "*neon_mov" [(set (match_operand:VDX 0 "nonimmediate_operand" - "=w,Un,w, w, ?r,?w,?r, ?Us") + "=w,Un,w, w, ?r,?w,?r, ?Us,*r") (match_operand:VDX 1 "general_operand" - " w,w, Dn,Uni, w, r, Usi,r"))] + " w,w, Dn,Uni, w, r, Usi,r,*r"))] "TARGET_NEON && (register_operand (operands[0], mode) || register_operand (operands[1], mode))" @@ -57,16 +57,17 @@ case 2: gcc_unreachable (); case 4: return "vmov\t%Q0, %R0, %P1 @ "; case 5: return "vmov\t%P0, %Q1, %R1 @ "; + case 8: return "#"; default: return output_move_double (operands, true, NULL); } } [(set_attr "type" "neon_move,neon_store1_1reg,neon_move,\ neon_load1_1reg, neon_to_gp,neon_from_gp,\ - neon_load1_2reg, neon_store1_2reg") - (set_attr "length" "4,4,4,4,4,4,8,8") - (set_attr "arm_pool_range" "*,*,*,1020,*,*,1020,*") - (set_attr "thumb2_pool_range" "*,*,*,1018,*,*,1018,*") - (set_attr "neg_pool_range" "*,*,*,1004,*,*,1004,*")]) + neon_load1_2reg, neon_store1_2reg, multiple") + (set_attr "length" "4,4,4,4,4,4,8,8,8") + (set_attr "arm_pool_range" "*,*,*,1020,*,*,1020,*,*") + (set_attr "thumb2_pool_range" "*,*,*,1018,*,*,1018,*,*") + (set_attr "neg_pool_range" "*,*,*,1004,*,*,1004,*,*")]) (define_insn "*neon_mov" [(set (match_operand:VQXMOV 0 "nonimmediate_operand" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 152dce3fa8e..6c6fe276221 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2019-02-07 Tamar Christina + + PR/target 88850 + * gcc.target/arm/pr88850.c: New test. + 2019-02-07 Alexandre Oliva PR c++/86218 diff --git a/gcc/testsuite/gcc.target/arm/pr88850.c b/gcc/testsuite/gcc.target/arm/pr88850.c new file mode 100644 index 00000000000..66d0e9e620a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr88850.c @@ -0,0 +1,22 @@ +/* PR target/88850 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv7-a -mfloat-abi=softfp -mfpu=neon -fdump-rtl-final" } */ +/* { dg-require-effective-target arm_neon_ok } */ + +typedef __builtin_neon_qi int8x8_t __attribute__ ((__vector_size__ (8))); +void bar (int8x8_t, int8x8_t); + +void +foo (int8x8_t x, int8x8_t y) +{ + bar (y, x); +} + +void foo2 (int8x8_t x) +{ + int8x8_t y; + bar (y, x); +} + +/* Check that these 64-bit moves are done in SI. */ +/* { dg-final { scan-rtl-dump "_movsi_vfp" "final" } } */ -- 2.30.2