From 4fec3a85cd7d0fcd35f958bfc89090df25f7de3c Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Thu, 29 Jul 2021 12:35:22 -0400
Subject: [PATCH] genrtlil: add width detection for AST_PREFIX nodes

---
 frontends/ast/genrtlil.cc       |  8 ++++++++
 tests/simple/loop_prefix_case.v | 18 ++++++++++++++++++
 2 files changed, 26 insertions(+)
 create mode 100644 tests/simple/loop_prefix_case.v

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 90d5f1bba..45aab9d8e 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -993,6 +993,14 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 		break;
 	}
 
+	case AST_PREFIX:
+		// Prefix nodes always resolve to identifiers in generate loops, so we
+		// can simply perform the resolution to determine the sign and width.
+		simplify(true, false, false, 1, -1, false, false);
+		log_assert(type == AST_IDENTIFIER);
+		detectSignWidthWorker(width_hint, sign_hint, found_real);
+		break;
+
 	case AST_FCALL:
 		if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq") {
 			if (GetSize(children) == 1) {
diff --git a/tests/simple/loop_prefix_case.v b/tests/simple/loop_prefix_case.v
new file mode 100644
index 000000000..7ee28ed70
--- /dev/null
+++ b/tests/simple/loop_prefix_case.v
@@ -0,0 +1,18 @@
+module top(
+	input wire x,
+	output reg y
+);
+	localparam I = 1;
+	genvar i;
+	generate
+		for (i = 0; i < 1; i = i + 1) begin : blk
+			wire [i:i] z = x;
+		end
+	endgenerate
+	always @* begin
+		case (blk[I - 1].z)
+			1: y = 0;
+			0: y = 1;
+		endcase
+	end
+endmodule
-- 
2.30.2