From 501af3e7715b2f188af5529c671966a3cc332c16 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 10 Feb 2022 15:53:58 +0000 Subject: [PATCH] attempting to get libre-soc boot on ulx3s-85f --- README.txt | 4 +++- versa_ecp5.py | 8 ++++---- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/README.txt b/README.txt index b7eb141..4dd5e0d 100644 --- a/README.txt +++ b/README.txt @@ -17,6 +17,8 @@ same thing: first build libresoc.v and copy it to the libresoc/ directory # arty a7 build export PATH=$PATH:/usr/local/symbiflow/bin/:/usr/local/symbiflow/vtr/bin/ -./versa_ecp5.py --sys-clk-freq=100e6 --build --fpga=artya7100t \ +./versa_ecp5.py --sys-clk-freq=25e6 --build --fpga=artya7100t \ + --toolchain=symbiflow +./versa_ecp5.py --sys-clk-freq=25e6 --load --fpga=artya7100t \ --toolchain=symbiflow diff --git a/versa_ecp5.py b/versa_ecp5.py index a3772e7..42ff88f 100755 --- a/versa_ecp5.py +++ b/versa_ecp5.py @@ -84,6 +84,7 @@ class ULX3S85FTestSoC(ulx3s.BaseSoC): kwargs["integrated_rom_size"] = 0x10000 #kwargs["integrated_main_ram_size"] = 0x1000 kwargs["csr_data_width"] = 32 + kwargs['csr_address_width'] = 15 # limit to 0x8000 kwargs["l2_size"] = 0 #bus_data_width = 16, @@ -126,9 +127,9 @@ class ArtyTestSoC(arty.BaseSoC): arty.BaseSoC.__init__(self, sys_clk_freq = sys_clk_freq, cpu_type = "external", - #cpu_cls = LibreSoC, - #cpu_variant = "standardjtag", - cpu_cls = Microwatt, + cpu_cls = LibreSoC, + cpu_variant = "standardjtag", + #cpu_cls = Microwatt, variant = "a7-100", toolchain = "symbiflow", **kwargs) @@ -160,7 +161,6 @@ def main(): **soc_sdram_argdict(args)) elif args.fpga == "ulx3s85f": - trellis_args(parser) soc = ULX3S85FTestSoC(sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args)) -- 2.30.2