From 501b94526080fcd08a413bdb41e05540cc16fe44 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 16 Oct 2020 19:28:36 +0100 Subject: [PATCH] manually run coresync clock for test issuer --- src/soc/simple/test/test_issuer.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py index 012e5b19..f38bbcf6 100644 --- a/src/soc/simple/test/test_issuer.py +++ b/src/soc/simple/test/test_issuer.py @@ -4,7 +4,7 @@ related bugs: * https://bugs.libre-soc.org/show_bug.cgi?id=363 """ -from nmigen import Module, Signal, Cat +from nmigen import Module, Signal, Cat, ClockSignal # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell # Also, check out the cxxsim nmigen branch, and latest yosys from git @@ -164,6 +164,10 @@ class TestRunner(FHDLTestCase): simdec2 = PowerDecode2(simdec) m.submodules.simdec2 = simdec2 # pain in the neck + # run core clock at same rate as test clock + intclk = ClockSignal("coresync") + comb += intclk.eq(ClockSignal()) + comb += issuer.pc_i.data.eq(pc_i) # nmigen Simulation -- 2.30.2