From 5025354342d8e92f200b9c0c0a04f96a53d7f0e3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 28 Nov 2023 20:41:01 +0000 Subject: [PATCH] fix elwidth overrides when sw=8 the way that XLEN works is it must be MAX(sw,dw) which is not what was happening, it was fixed at sw (source width) --- src/openpower/decoder/isa/caller.py | 19 +++++++++++-------- src/openpower/test/alu/svp64_cases.py | 27 +++++++++++++++++++++++++++ 2 files changed, 38 insertions(+), 8 deletions(-) diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index 299df0c2..9a8c2481 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -2154,7 +2154,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop): ew_src = 8 << (3-int(ew_src)) # convert to bitlength ew_dst = 8 << (3-int(ew_dst)) # convert to bitlength xlen = max(ew_src, ew_dst) - log("elwdith", ew_src, ew_dst) + log("elwidth", ew_src, ew_dst) log("XLEN:", self.is_svp64_mode, xlen) # look up instruction in ISA.instrs, prepare namespace @@ -2250,7 +2250,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop): elif name in spr_byname: inputs[name] = self.spr[name] else: - regval = (yield from self.get_input(name, ew_src)) + regval = (yield from self.get_input(name, ew_src, xlen)) log("regval name", name, regval) inputs[name] = regval @@ -2550,7 +2550,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop): else: self.namespace['D'] = imm - def get_input(self, name, ew_src): + def get_input(self, name, ew_src, xlen): # using PowerDecoder2, first, find the decoder index. # (mapping name RA RB RC RS to in1, in2, in3) regnum, is_vec = yield from get_idx_in(self.dec2, name, True) @@ -2577,14 +2577,17 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop): if not self.is_svp64_mode or not self.pred_src_zero: log('reading reg %s %s' % (name, str(regnum)), is_vec) if name in fregs: - reg_val = SelectableInt(self.fpr(base, is_vec, offs, ew_src)) - log("read reg %d/%d: 0x%x" % (base, offs, reg_val.value), - kind=LogType.InstrInOuts) + fval = self.fpr(base, is_vec, offs, ew_src) + reg_val = SelectableInt(fval) + assert ew_src == XLEN, "TODO fix elwidth conversion" self.trace("r:FPR:%d:%d:%d " % (base, offs, ew_src)) + log("read fp reg %d/%d: 0x%x" % (base, offs, reg_val.value), + kind=LogType.InstrInOuts) elif name is not None: - reg_val = SelectableInt(self.gpr(base, is_vec, offs, ew_src)) + gval = self.gpr(base, is_vec, offs, ew_src) + reg_val = SelectableInt(gval.value, bits=xlen) self.trace("r:GPR:%d:%d:%d " % (base, offs, ew_src)) - log("read reg %d/%d: 0x%x" % (base, offs, reg_val.value), + log("read int reg %d/%d: 0x%x" % (base, offs, reg_val.value), kind=LogType.InstrInOuts) else: log('zero input reg %s %s' % (name, str(regnum)), is_vec) diff --git a/src/openpower/test/alu/svp64_cases.py b/src/openpower/test/alu/svp64_cases.py index b86a1d12..638da111 100644 --- a/src/openpower/test/alu/svp64_cases.py +++ b/src/openpower/test/alu/svp64_cases.py @@ -34,6 +34,33 @@ class SVP64ALUElwidthTestCase(TestAccumulatorBase): initial_svstate=svstate, expected=e) + def case_2_sv_add_sw8(self): + """>>> lst = ['sv.add/sw=8 *1, *5, *9'] + """ + isa = SVP64Asm(['sv.add/sw=8 *1, *5, *9']) + lst = list(isa) + print("listing", lst) + + # initial values in GPR regfile + initial_regs = [0] * 32 + initial_regs[9] = 0x1220 + initial_regs[5] = 0x43ff + # SVSTATE (in this case, VL=2) + svstate = SVP64State() + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) + + # expected: each 8-bit add is completely independent + gprs = deepcopy(initial_regs) + gprs[1] = 0x11f # 0x20+0xff = 0x11f (64-bit) + gprs[2] = 0x55 # 0x12+0x43 = 0x55 (64-bit) + e = ExpectedState(pc=8, int_regs=gprs) + + self.add_case(Program(lst, bigendian), initial_regs, + initial_svstate=svstate, expected=e) + + def case_2_sv_add_ew32(self): """>>> lst = ['sv.add/w=32 *1, *5, *9'] """ -- 2.30.2