From 503402e769d72d0d62095d7d6d50972fc1056995 Mon Sep 17 00:00:00 2001
From: Staf Verhaegen <staf@stafverhaegen.be>
Date: Thu, 4 Jul 2019 17:13:56 +0200
Subject: [PATCH] vendor.xilinx_{7series,spartan6}: Support extra VHDL files.

---
 nmigen/vendor/xilinx_7series.py  | 2 +-
 nmigen/vendor/xilinx_spartan6.py | 3 +++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py
index 3c43b08..7b06cdb 100644
--- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -55,7 +55,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         "{{name}}.tcl": r"""
             # {{autogenerated}}
             create_project -force -name {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speed}}
-            {% for file in platform.iter_extra_files(".v", ".sv") -%}
+            {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
                 add_files {{file}}
             {% endfor %}
             add_files {{name}}.v
diff --git a/nmigen/vendor/xilinx_spartan6.py b/nmigen/vendor/xilinx_spartan6.py
index 4a0d3a6..7ac360a 100644
--- a/nmigen/vendor/xilinx_spartan6.py
+++ b/nmigen/vendor/xilinx_spartan6.py
@@ -57,6 +57,9 @@ class XilinxSpartan6Platform(TemplatedPlatform):
         """,
         "{{name}}.prj": r"""
             # {{autogenerated}}
+            {% for file in platform.iter_extra_files(".vhd", ".vhdl") -%}
+                vhdl work {{file}}
+            {% endfor %}
             {% for file in platform.iter_extra_files(".v") -%}
                 verilog work {{file}}
             {% endfor %}
-- 
2.30.2