From 503ec180c61089c2a1677296021ecdcec721068e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 10 Jul 2021 12:10:08 +0100 Subject: [PATCH] add more generic detection of FFT mode, really needs to be a new column in CSV file for Out2 --- src/openpower/decoder/power_decoder2.py | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index b6978de0..f2891dbc 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -489,13 +489,13 @@ class DecodeOut2(Elaboratable): comb += self.fast_out3.data.eq(FastRegsEnum.SVSRR0) # SVSRR0 comb += self.fast_out3.ok.eq(1) - # SVP64 FFT mode, FP mul-add: 2nd output reg (FRS) same as FRT - # will be offset by VL in hardware - with m.Case(MicrOp.OP_FP_MADD): - with m.If(self.svp64_fft_mode): - comb += self.reg_out.data.eq(self.dec.FRT) - comb += self.reg_out.ok.eq(1) - comb += self.fp_madd_en.eq(1) + # SVP64 FFT mode, FP mul-add: 2nd output reg (FRS) same as FRT + # will be offset by VL in hardware + #with m.Case(MicrOp.OP_FP_MADD): + with m.If(self.svp64_fft_mode): + comb += self.reg_out.data.eq(self.dec.FRT) + comb += self.reg_out.ok.eq(1) + comb += self.fp_madd_en.eq(1) return m @@ -1025,9 +1025,9 @@ class PowerDecodeSubset(Elaboratable): bitrev = rm_dec.ldstmode == SVP64LDSTmode.BITREVERSE comb += self.use_svp64_ldst_dec.eq(bitrev) # detect if SVP64 FFT mode enabled (really bad hack) - xo = Signal(2) # 2 bits from Major 59 XO field == 0b00XXX - comb += xo.eq(self.dec.opcode_in[4:6]) - comb += self.use_svp64_fft.eq((major == 59) & (xo == 0b00)) + xo = Signal(1) # 1 bit from Major 59 XO field == 0b0XXXX + comb += xo.eq(self.dec.opcode_in[5]) + comb += self.use_svp64_fft.eq((major == 59) & (xo == 0b0)) # decoded/selected instruction flags comb += self.do_copy("data_len", self.op_get("ldst_len")) -- 2.30.2