From 50487d7978c5cafd044cf58c5e705175f5a671a9 Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Thu, 12 Nov 2015 14:46:52 +0000 Subject: [PATCH] [AArch64] Add extra tuning parameters for target processors gcc/ * config/aarch64/aarch64-protos.h (tune_params): Add new members "max_case_values" and "cache_line_size". * config/aarch64/aarch64.c (aarch64_case_values_threshold): New function. (aarch64_override_options_internal): Tune heuristics based on new members in "tune_params". (TARGET_CASE_VALUES_THRESHOLD): Define macro. From-SVN: r230261 --- gcc/ChangeLog | 10 ++++++++ gcc/config/aarch64/aarch64-protos.h | 4 ++++ gcc/config/aarch64/aarch64.c | 36 +++++++++++++++++++++++++++++ 3 files changed, 50 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ecd37115d82..27a1e9ec267 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2015-11-12 Evandro Menezes + + * config/aarch64/aarch64-protos.h (tune_params): Add new members + "max_case_values" and "cache_line_size". + * config/aarch64/aarch64.c (aarch64_case_values_threshold): New + function. + (aarch64_override_options_internal): Tune heuristics based on new + members in "tune_params". + (TARGET_CASE_VALUES_THRESHOLD): Define macro. + 2015-11-12 Richard Biener PR tree-optimization/68306 diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 7c74f585fb8..9000d67a9d1 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -195,6 +195,10 @@ struct tune_params int vec_reassoc_width; int min_div_recip_mul_sf; int min_div_recip_mul_df; + /* Value for aarch64_case_values_threshold; or 0 for the default. */ + unsigned int max_case_values; + /* Value for PARAM_L1_CACHE_LINE_SIZE; or 0 to use the default. */ + unsigned int cache_line_size; /* An enum specifying how to take into account CPU autoprefetch capabilities during instruction scheduling: diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 7d6dfc342b8..5ec7f08ca96 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -356,6 +356,8 @@ static const struct tune_params generic_tunings = 1, /* vec_reassoc_width. */ 2, /* min_div_recip_mul_sf. */ 2, /* min_div_recip_mul_df. */ + 0, /* max_case_values. */ + 0, /* cache_line_size. */ tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */ (AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */ }; @@ -379,6 +381,8 @@ static const struct tune_params cortexa53_tunings = 1, /* vec_reassoc_width. */ 2, /* min_div_recip_mul_sf. */ 2, /* min_div_recip_mul_df. */ + 0, /* max_case_values. */ + 0, /* cache_line_size. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ (AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */ }; @@ -402,6 +406,8 @@ static const struct tune_params cortexa57_tunings = 1, /* vec_reassoc_width. */ 2, /* min_div_recip_mul_sf. */ 2, /* min_div_recip_mul_df. */ + 0, /* max_case_values. */ + 0, /* cache_line_size. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ (AARCH64_EXTRA_TUNE_RENAME_FMA_REGS | AARCH64_EXTRA_TUNE_RECIP_SQRT) /* tune_flags. */ @@ -426,6 +432,8 @@ static const struct tune_params cortexa72_tunings = 1, /* vec_reassoc_width. */ 2, /* min_div_recip_mul_sf. */ 2, /* min_div_recip_mul_df. */ + 0, /* max_case_values. */ + 0, /* cache_line_size. */ tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */ (AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */ }; @@ -448,6 +456,8 @@ static const struct tune_params thunderx_tunings = 1, /* vec_reassoc_width. */ 2, /* min_div_recip_mul_sf. */ 2, /* min_div_recip_mul_df. */ + 0, /* max_case_values. */ + 0, /* cache_line_size. */ tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */ (AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */ }; @@ -470,6 +480,8 @@ static const struct tune_params xgene1_tunings = 1, /* vec_reassoc_width. */ 2, /* min_div_recip_mul_sf. */ 2, /* min_div_recip_mul_df. */ + 0, /* max_case_values. */ + 0, /* cache_line_size. */ tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */ (AARCH64_EXTRA_TUNE_RECIP_SQRT) /* tune_flags. */ }; @@ -3240,6 +3252,20 @@ aarch64_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) return aarch64_tls_referenced_p (x); } +/* Implement TARGET_CASE_VALUES_THRESHOLD. */ + +static unsigned int +aarch64_case_values_threshold (void) +{ + /* Use the specified limit for the number of cases before using jump + tables at higher optimization levels. */ + if (optimize > 2 + && selected_cpu->tune->max_case_values != 0) + return selected_cpu->tune->max_case_values; + else + return default_case_values_threshold (); +} + /* Return true if register REGNO is a valid index register. STRICT_P is true if REG_OK_STRICT is in effect. */ @@ -7782,6 +7808,13 @@ aarch64_override_options_internal (struct gcc_options *opts) opts->x_param_values, global_options_set.x_param_values); + /* Set the L1 cache line size. */ + if (selected_cpu->tune->cache_line_size != 0) + maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, + selected_cpu->tune->cache_line_size, + opts->x_param_values, + global_options_set.x_param_values); + aarch64_override_options_after_change_1 (opts); } @@ -13526,6 +13559,9 @@ aarch64_promoted_type (const_tree t) #undef TARGET_CANNOT_FORCE_CONST_MEM #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem +#undef TARGET_CASE_VALUES_THRESHOLD +#define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold + #undef TARGET_CONDITIONAL_REGISTER_USAGE #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage -- 2.30.2