From 50569deeb552da3ae4ee075dc071f2b87947029f Mon Sep 17 00:00:00 2001 From: Jackie Smith Cashion Date: Wed, 31 Jul 1996 13:43:51 +0000 Subject: [PATCH] Wed Jul 31 14:39:27 1996 James G. Smith * arm-opc.h: (arm_opcodes): Added halfword and sign-extension memory transfer instructions. Add new format string entries %h and %s. * arm-dis.c: (print_insn_arm): Provide decoding of the new formats %h and %s. --- opcodes/ChangeLog | 7 +++++++ opcodes/arm-opc.h | 4 ++++ 2 files changed, 11 insertions(+) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ebcbec7659d..df3c940126c 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +Wed Jul 31 14:39:27 1996 James G. Smith + + * arm-opc.h: (arm_opcodes): Added halfword and sign-extension + memory transfer instructions. Add new format string entries %h and %s. + * arm-dis.c: (print_insn_arm): Provide decoding of the new + formats %h and %s. + start-sanitize-d10v Fri Jul 26 11:45:04 1996 Martin M. Hunt diff --git a/opcodes/arm-opc.h b/opcodes/arm-opc.h index 33f5daa90d2..82ad208424d 100644 --- a/opcodes/arm-opc.h +++ b/opcodes/arm-opc.h @@ -39,8 +39,10 @@ struct arm_opcode { %?ab print a if bit is one else print b %p print 'p' iff bits 12-15 are 15 %t print 't' iff bit 21 set and bit 24 clear + %h print 'h' iff bit 5 set, else print 'b' %o print operand2 (immediate or register + shift) %a print address for ldr/str instruction + %s print address for ldr/str halfword/signextend instruction %b print branch destination %A print address for ldc/stc/ldf/stf instruction %m print register mask for ldm/stm instruction @@ -58,6 +60,8 @@ static struct arm_opcode arm_opcodes[] = { {0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"}, {0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, {0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, + {0x00000090, 0x0e100090, "str%c%6's%h\t%12-15r, %s"}, + {0x00100090, 0x0e100090, "ldr%c%6's%h\t%12-15r, %s"}, {0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"}, {0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"}, {0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"}, -- 2.30.2