From 5064f00d605ccd16a169454fdede5f9e77591bce Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Sat, 23 Jul 2022 18:38:12 -0300 Subject: [PATCH] Remove unused Minerva CPU import from headless examples The headless examples do not use an embedded CPU. Instead, the host computer commands the Gram controller via a Wishbone-UART bridge. --- examples/headless-ecpix5.py | 1 - examples/headless-versa-85.py | 1 - 2 files changed, 2 deletions(-) diff --git a/examples/headless-ecpix5.py b/examples/headless-ecpix5.py index 8e1bd20..da7333b 100644 --- a/examples/headless-ecpix5.py +++ b/examples/headless-ecpix5.py @@ -4,7 +4,6 @@ from nmigen import * from nmigen.lib.cdc import ResetSynchronizer from nmigen_soc import wishbone, memory -from lambdasoc.cpu.minerva import MinervaCPU from lambdasoc.periph.intc import GenericInterruptController from lambdasoc.periph.serial import AsyncSerialPeripheral from lambdasoc.periph.sram import SRAMPeripheral diff --git a/examples/headless-versa-85.py b/examples/headless-versa-85.py index 3050f89..371a868 100644 --- a/examples/headless-versa-85.py +++ b/examples/headless-versa-85.py @@ -5,7 +5,6 @@ from nmigen import * from nmigen.lib.cdc import ResetSynchronizer from nmigen_soc import wishbone, memory -from lambdasoc.cpu.minerva import MinervaCPU from lambdasoc.periph.intc import GenericInterruptController from lambdasoc.periph.serial import AsyncSerialPeripheral from lambdasoc.periph.sram import SRAMPeripheral -- 2.30.2