From 508948f55c598a86c2fc401ef49f5c08da22c1f5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 19 May 2020 22:55:54 +0100 Subject: [PATCH] output ilang to branch_pipeline.il for branch --- src/soc/fu/branch/test/test_pipe_caller.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py index 898afa8d..8666a416 100644 --- a/src/soc/fu/branch/test/test_pipe_caller.py +++ b/src/soc/fu/branch/test/test_pipe_caller.py @@ -104,7 +104,7 @@ class BranchTestCase(FHDLTestCase): pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec)) alu = BranchBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) - with open("logical_pipeline.il", "w") as f: + with open("branch_pipeline.il", "w") as f: f.write(vl) -- 2.30.2