From 50a2929e443c19d90a53c4b50c7782acc07a74f1 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 19 May 2018 19:22:07 +0100 Subject: [PATCH] more slides --- simple_v_extension/simple_v_chennai_2018.tex | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex index d2cf1114b..e63c56107 100644 --- a/simple_v_extension/simple_v_chennai_2018.tex +++ b/simple_v_extension/simple_v_chennai_2018.tex @@ -182,7 +182,7 @@ for (int i = 0; i < VL; ++i) \item SIMD slightly more complex (case above is elwidth = default) \item If s1 and s2 both scalars, Standard branch occurs \item Predication stored in integer regfile as a bitfield - \item x + \item Scalar-vector and vector-vector supported \end{itemize} \end{frame} @@ -219,6 +219,22 @@ for (int i = 0; i < VL; ++i) } +\frame{\frametitle{Opcodes, compared to RVV} + + \begin{itemize} + \item All integer and FP opcodes removed (no CLIP!)\vspace{10pt} + \item VMPOP, VFIRST etc. all removed (use xBitManip)\vspace{10pt} + \item VSLIDE removed (just redefine vector)\vspace{10pt} + \item VSETVL, VGETVL, VMERGE all stay\vspace{10pt} + \end{itemize} + Issues:\vspace{10pt} + \begin{itemize} + \item VCLIP is not in RV*\vspace{10pt} + \item Vector copy: use C.MV (MV is a pseudo-op)\vspace{10pt} + \end{itemize} +} + + \frame{\frametitle{slide} \begin{itemize} -- 2.30.2