From 50a45192868f6dae7550bfa76d60f334fbf0c815 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Wed, 22 Nov 2023 14:35:23 +0000
Subject: [PATCH]

---
 nlnet_2023_svp64_riscv.mdwn | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/nlnet_2023_svp64_riscv.mdwn b/nlnet_2023_svp64_riscv.mdwn
index 6aae97155..17bc4a96c 100644
--- a/nlnet_2023_svp64_riscv.mdwn
+++ b/nlnet_2023_svp64_riscv.mdwn
@@ -54,10 +54,15 @@ EUR $50,000.
 * Assessment of application of Simple-V Vector Prefixing to SVP64,
   modernising the work already done four years ago under
   NLnet Grant 2019-10-012 <https://libre-soc.org/nlnet_2018/>
-* Implementing Simple-V 
+* Implementing Simple-V in the Libre-SOC Simulator, ISACaller.
 * Upgrading sv-spike which was completed four years ago with
   an early prototype Simple-V Specification
   <https://git.libre-soc.org/?p=riscv-isa-sim.git;a=shortlog;h=refs/heads/sv>
+* Adding a large comprehensive unit test base for the new instructions
+  which can then be tested against sv-spike as well as ISACaller.
+  Many of these were already written four years ago and need conversion
+  to the new format used in Libre-SOC
+  <https://git.libre-soc.org/?p=riscv-tests.git;a=shortlog;h=refs/heads/sv>
 * Research and assessment of ARM7 and i486 (both on opencores.org)
   as to their feasibility for applying Simple-V Prefixing
 
-- 
2.30.2