From 50acf4a72433a22bbe6a8162deb7b959370a0a15 Mon Sep 17 00:00:00 2001 From: whitequark Date: Thu, 3 Oct 2019 06:10:43 +0000 Subject: [PATCH] [breaking-change] Fix polarity of "dm" signal in "memory" resource. LB# and UB# enable writing their corresponding byte. The "m" in "dm" means mask; that is, logical high masks (prevents) the byte from being written. This means that it should use Pins(), not PinsN(), to get the behavior implied by "mask". --- nmigen_boards/resources/memory.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nmigen_boards/resources/memory.py b/nmigen_boards/resources/memory.py index 809035c..33976a7 100644 --- a/nmigen_boards/resources/memory.py +++ b/nmigen_boards/resources/memory.py @@ -90,7 +90,7 @@ def SRAMResource(*args, cs, oe=None, we, a, d, dm=None, attrs=None): io.append(Subsignal("a", Pins(a, dir="o"))) io.append(Subsignal("d", Pins(d, dir="io"))) if dm is not None: - io.append(Subsignal("dm", PinsN(dm, dir="o"))) # dm="LB# UB#" + io.append(Subsignal("dm", Pins(dm, dir="o"))) # dm="LB# UB#" if attrs is not None: io.append(attrs) return Resource.family(*args, default_name="sram", ios=io) -- 2.30.2