From 50b09de03320843660636c663629c649ab242321 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 2 Jan 2019 15:05:23 +0100 Subject: [PATCH] Fix VerificImporter asymmetric memories error message Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 61d9d593c..5280a2b9c 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1201,7 +1201,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se { RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetOutput()->Name())); if (memory->width != int(inst->Input2Size())) - log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name()); + log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetOutput()->Name()); RTLIL::SigSpec addr = operatorInput1(inst); RTLIL::SigSpec data = operatorInput2(inst); -- 2.30.2