From 50b1cbdd9153171adcea585ce852c7d50a3d15f7 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 22 May 2019 13:36:39 +0100
Subject: [PATCH] use shifter opcode

---
 src/experiment/alu_hier.py  |  9 ++++++---
 src/experiment/score6600.py | 15 ++++++++-------
 2 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/src/experiment/alu_hier.py b/src/experiment/alu_hier.py
index 847bc324..506f6e70 100644
--- a/src/experiment/alu_hier.py
+++ b/src/experiment/alu_hier.py
@@ -1,4 +1,4 @@
-from nmigen import Elaboratable, Signal, Module
+from nmigen import Elaboratable, Signal, Module, Const
 from nmigen.cli import main
 
 
@@ -40,13 +40,16 @@ class Multiplier(Elaboratable):
 
 class Shifter(Elaboratable):
     def __init__(self, width):
+        self.width = width
         self.a   = Signal(width)
-        self.b   = Signal(max=width)
+        self.b   = Signal(width)
         self.o   = Signal(width)
 
     def elaborate(self, platform):
         m = Module()
-        m.d.comb += self.o.eq(self.a << self.b)
+        btrunc = Signal(self.width)
+        m.d.comb += btrunc.eq(self.b & Const((1<<self.width)-1))
+        m.d.comb += self.o.eq(self.a >> btrunc)
         return m
 
 
diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index 4df31746..e3a56b7e 100644
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -327,17 +327,18 @@ class RegSim:
         self.regs = [0] * nregs
 
     def op(self, op, src1, src2, dest):
+        maxbits = (1 << self.rwidth) - 1
         src1 = self.regs[src1]
         src2 = self.regs[src2]
         if op == IADD:
-            val = (src1 + src2)
+            val = src1 + src2
         elif op == ISUB:
-            val = (src1 - src2)
+            val = src1 - src2
         elif op == IMUL:
-            val = (src1 * src2)
+            val = src1 * src2
         elif op == ISHF:
-            val = (src1 << (src2 & self.rwidth))
-        val &= ((1<<(self.rwidth))-1)
+            val = src1 >> (src2 & maxbits)
+        val &= maxbits
         self.regs[dest] = val
 
     def setval(self, dest, val):
@@ -391,7 +392,7 @@ def scoreboard_sim(dut, alusim):
         # create some instructions (some random, some regression tests)
         instrs = []
         if True:
-            for i in range(20):
+            for i in range(10):
                 src1 = randint(1, dut.n_regs-1)
                 src2 = randint(1, dut.n_regs-1)
                 while True:
@@ -403,7 +404,7 @@ def scoreboard_sim(dut, alusim):
                 #src2 = 3
                 #dest = 2
 
-                op = randint(0, 2)
+                op = randint(0, 3)
                 #op = i % 2
                 #op = 0
 
-- 
2.30.2