From 50b73fcde42694209997f01f9985dc5928a86fca Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Sun, 23 Sep 2007 19:20:01 +0000 Subject: [PATCH] mips.c (build_mips16_call_stub): On 64-bit targets, combine an SC return value into a single register. gcc/ * config/mips/mips.c (build_mips16_call_stub): On 64-bit targets, combine an SC return value into a single register. From-SVN: r128700 --- gcc/ChangeLog | 5 +++++ gcc/config/mips/mips.c | 13 +++++++++++++ 2 files changed, 18 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 639dc8e1b34..2837ede708b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2007-09-23 Richard Sandiford + + * config/mips/mips.c (build_mips16_call_stub): On 64-bit targets, + combine an SC return value into a single register. + 2007-09-23 Richard Sandiford * opth-gen.awk (target_flags_explicit): Declare. diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index e6b17a5f08c..39d5e371e6d 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -10055,6 +10055,19 @@ build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code) fprintf (asm_out_file, "\tmfc1\t%s,%s\n", reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]); + if (GET_MODE (retval) == SCmode && TARGET_64BIT) + { + /* On 64-bit targets, complex floats are returned in + a single GPR, such that "sd" on a suitably-aligned + target would store the value correctly. */ + fprintf (asm_out_file, "\tdsll\t%s,%s,32\n", + reg_names[GP_REG_FIRST + 2 + TARGET_LITTLE_ENDIAN], + reg_names[GP_REG_FIRST + 2 + TARGET_LITTLE_ENDIAN]); + fprintf (asm_out_file, "\tor\t%s,%s,%s\n", + reg_names[GP_REG_FIRST + 2], + reg_names[GP_REG_FIRST + 2], + reg_names[GP_REG_FIRST + 3]); + } break; case DCmode: -- 2.30.2