From 50c2713726f007b988502ed5e7073fae11409853 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Thu, 3 Sep 2015 17:08:16 +0300 Subject: [PATCH] i965: Adjust gen check in can_do_pipelined_register_writes MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Allow for pipelined register writes for gen < 7. v2: * Split from another patch and adjust comment (jljusten) Reviewed-by: Jordan Justen Reviewed-by: Kristian Høgsberg --- src/mesa/drivers/dri/i965/intel_extensions.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index bec318ffa3d..8a1ec324e2c 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++ b/src/mesa/drivers/dri/i965/intel_extensions.c @@ -38,8 +38,11 @@ static bool can_do_pipelined_register_writes(struct brw_context *brw) { - /* Supposedly, Broadwell just works. */ - if (brw->gen >= 8) + /** + * gen >= 8 specifically allows these writes. gen <= 6 also + * doesn't block them. + */ + if (brw->gen != 7) return true; static int result = -1; -- 2.30.2