From 50c791cfd4f3458d96f45ab3a81b599f4d7580d1 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 5 Jan 2022 23:53:24 +0000 Subject: [PATCH] add eieio instruction as a NOP to minor 31 csv --- openpower/isatables/minor_31.csv | 1 + src/openpower/decoder/power_enums.py | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/openpower/isatables/minor_31.csv b/openpower/isatables/minor_31.csv index dcadd41c..c4f4c45f 100644 --- a/openpower/isatables/minor_31.csv +++ b/openpower/isatables/minor_31.csv @@ -46,6 +46,7 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 0b1111101001,DIV,OP_DIV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC,0,0,divdo,XO, 0b0111101011,DIV,OP_DIV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC,0,0,divw,XO, 0b1111101011,DIV,OP_DIV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC,0,0,divwo,XO, +0b1101010110,ALU,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,eieio,X, 0b0100011100,LOGICAL,OP_XOR,RS,RB,NONE,RA,NONE,CR0,0,1,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,eqv,X, 0b1110111010,ALU,OP_EXTS,RS,NONE,NONE,RA,NONE,CR0,0,0,ZERO,0,is1B,0,0,0,0,0,0,RC,0,0,extsb,X, 0b1110011010,ALU,OP_EXTS,RS,NONE,NONE,RA,NONE,CR0,0,0,ZERO,0,is2B,0,0,0,0,0,0,RC,0,0,extsh,X, diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index 4d62d068..0e1517dd 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -272,7 +272,7 @@ _insns = [ "divd", "divde", "divdeo", "divdeu", "divdeuo", "divdo", "divdu", "divduo", "divw", "divwe", "divweo", "divweu", "divweuo", "divwo", "divwu", "divwuo", - "eqv", + "eieio", "eqv", "extsb", "extsh", "extsw", "extswsli", "fadd", "fadds", "fsub", "fsubs", # FP add / sub "fcfids", "fcfidus", "fsqrts", "fres", "frsqrtes", # FP stuff -- 2.30.2