From 50dbc469179f0d8bf310f2cf180b17be0ea1c650 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 24 Feb 2019 09:27:30 +0000 Subject: [PATCH] experimenting with dual add --- src/add/dual_add_experiment.py | 3 +++ src/add/fpbase.py | 9 ++++++--- src/add/test_dual.py | 31 ++++++++++++++++++++++--------- src/add/unit_test_single.py | 8 +++----- 4 files changed, 34 insertions(+), 17 deletions(-) diff --git a/src/add/dual_add_experiment.py b/src/add/dual_add_experiment.py index a70c9335..815192c4 100644 --- a/src/add/dual_add_experiment.py +++ b/src/add/dual_add_experiment.py @@ -36,6 +36,7 @@ class ALU: self.b = FPOp(width) self.c = FPOp(width) self.z = FPOp(width) + self.int_stb = Signal() self.add1 = FPADD(width) self.add2 = FPADD(width) @@ -54,6 +55,8 @@ class ALU: m.d.comb += self.add2.in_b.chain_from(self.add1.out_z) # join output from add2 to z: z = add2.out_z m.d.comb += self.z.chain_from(self.add2.out_z) + # get at add1's stb signal + m.d.comb += self.int_stb.eq(self.add1.out_z.stb) #with m.If(self.op): # m.d.comb += self.o.eq(self.sub.o) #with m.Else(): diff --git a/src/add/fpbase.py b/src/add/fpbase.py index 6a135705..5bf8e8c4 100644 --- a/src/add/fpbase.py +++ b/src/add/fpbase.py @@ -339,12 +339,15 @@ class FPOp: self.width = width self.v = Signal(width) - self.stb = Signal() + self.stb = Signal(reset=0) self.ack = Signal() - def chain_from(self, in_op): + def chain_from(self, in_op, extra=None): + stb = in_op.stb + if extra is not None: + stb = stb & extra return [self.v.eq(in_op.v), # receive value - self.stb.eq(in_op.stb), # receive STB + self.stb.eq(stb), # receive STB in_op.ack.eq(self.ack), # send ACK ] diff --git a/src/add/test_dual.py b/src/add/test_dual.py index 55facb12..8e3a9d84 100644 --- a/src/add/test_dual.py +++ b/src/add/test_dual.py @@ -4,13 +4,6 @@ from dual_add_experiment import ALU def get_case(dut, a, b, c): - yield dut.c.v.eq(c) - yield dut.c.stb.eq(1) - yield - yield - c_ack = (yield dut.c.ack) - assert c_ack == 0 - yield dut.a.v.eq(a) yield dut.a.stb.eq(1) yield @@ -25,6 +18,20 @@ def get_case(dut, a, b, c): b_ack = (yield dut.b.ack) assert b_ack == 0 + while True: + out_z_stb = (yield dut.int_stb) + if not out_z_stb: + yield + continue + break + + yield dut.c.v.eq(c) + yield dut.c.stb.eq(1) + yield + yield + c_ack = (yield dut.c.ack) + assert c_ack == 0 + while True: yield out_z_stb = (yield dut.z.stb) @@ -33,13 +40,19 @@ def get_case(dut, a, b, c): out_z = yield dut.z.v - yield dut.z.ack.eq(1) + yield dut.z.ack.eq(0) yield dut.a.stb.eq(0) yield dut.b.stb.eq(0) yield dut.c.stb.eq(0) yield yield - yield dut.z.ack.eq(0) + yield + yield + yield + yield + yield dut.z.ack.eq(1) + yield + yield yield yield break diff --git a/src/add/unit_test_single.py b/src/add/unit_test_single.py index c6d7861f..ca5c14aa 100644 --- a/src/add/unit_test_single.py +++ b/src/add/unit_test_single.py @@ -53,16 +53,14 @@ def get_case(dut, a, b): out_z_stb = (yield dut.out_z.stb) if not out_z_stb: continue + out_z = yield dut.out_z.v + yield dut.out_z.ack.eq(0) yield dut.in_a.stb.eq(0) yield dut.in_b.stb.eq(0) - yield dut.out_z.ack.eq(1) - yield - yield dut.out_z.ack.eq(0) - yield yield + yield dut.out_z.ack.eq(1) break - out_z = yield dut.out_z.v return out_z def check_case(dut, a, b, z): -- 2.30.2