From 50dc4eedfede767f6c3bc1430c514619c56a889e Mon Sep 17 00:00:00 2001 From: Andreas Krebbel Date: Thu, 2 Feb 2017 12:18:52 +0000 Subject: [PATCH] S/390: Add missing comments listing mnemonics. These were useful in the past but are currently lacking on a couple of patterns. Fixed with this patch. gcc/ChangeLog: 2017-02-02 Andreas Krebbel * config/s390/s390.md: Add missing comments with the expanded mnemonics. * config/s390/vector.md: Likewise. * config/s390/vx-builtins.md: Likewise. From-SVN: r245122 --- gcc/ChangeLog | 7 +++++++ gcc/config/s390/s390.md | 7 +++++++ gcc/config/s390/vector.md | 9 +++++++++ gcc/config/s390/vx-builtins.md | 18 ++++++++++++++++++ 4 files changed, 41 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 26da5e89cd7..a083ac69991 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2017-02-02 Andreas Krebbel + + * config/s390/s390.md: Add missing comments with the expanded + mnemonics. + * config/s390/vector.md: Likewise. + * config/s390/vx-builtins.md: Likewise. + 2017-02-02 Jakub Jelinek PR target/79197 diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index e47c2e90a65..9bbd7e0dc30 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -4095,6 +4095,7 @@ operands[6] = operands[0]; }) +; rosbg, rxsbg (define_insn "*rsbg__noshift" [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") (IXOR:GPR @@ -4106,6 +4107,7 @@ "rsbg\t%0,%1,%2,%2,0" [(set_attr "op_type" "RIE")]) +; rosbg, rxsbg (define_insn "*rsbg_di_rotl" [(set (match_operand:DI 0 "nonimmediate_operand" "=d") (IXOR:DI @@ -4120,6 +4122,7 @@ "rsbg\t%0,%1,%2,%2,%b3" [(set_attr "op_type" "RIE")]) +; rosbg, rxsbg (define_insn "*rsbg__srl_bitmask" [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") (IXOR:GPR @@ -4136,6 +4139,7 @@ "rsbg\t%0,%1,%2,%2,64-%3" [(set_attr "op_type" "RIE")]) +; rosbg, rxsbg (define_insn "*rsbg__sll_bitmask" [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") (IXOR:GPR @@ -4155,6 +4159,7 @@ ;; unsigned {int,long} a, b ;; a = a | (b << const_int) ;; a = a ^ (b << const_int) +; rosbg, rxsbg (define_insn "*rsbg__sll" [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") (IXOR:GPR @@ -4170,6 +4175,7 @@ ;; unsigned {int,long} a, b ;; a = a | (b >> const_int) ;; a = a ^ (b >> const_int) +; rosbg, rxsbg (define_insn "*rsbg__srl" [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") (IXOR:GPR @@ -10671,6 +10677,7 @@ ; FIXME: There is also mvcin but we cannot use it since src and target ; may overlap. +; lrvr, lrv, strv, lrvgr, lrvg, strvg (define_insn "bswap2" [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T") (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))] diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index d8c56d519d8..c4bbffce55e 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -144,6 +144,7 @@ (include "vx-builtins.md") ; Full HW vector size moves +; vgmb, vgmh, vgmf, vgmg, vrepib, vrepih, vrepif, vrepig (define_insn "mov" [(set (match_operand:V_128 0 "nonimmediate_operand" "=v,v,R, v, v, v, v, v,v,d") (match_operand:V_128 1 "general_operand" " v,R,v,j00,jm1,jyy,jxx,jKK,d,v"))] @@ -329,6 +330,7 @@ ; FIXME: A target memory operand seems to be useful otherwise we end ; up with vl vlvgg vst. Shouldn't the middle-end be able to handle ; that itself? +; vlvgb, vlvgh, vlvgf, vlvgg, vleb, vleh, vlef, vleg, vleib, vleih, vleif, vleig (define_insn "*vec_set" [(set (match_operand:V 0 "register_operand" "=v,v,v") (unspec:V [(match_operand: 1 "general_operand" "d,R,K") @@ -344,6 +346,7 @@ vlei\t%v0,%1,%2" [(set_attr "op_type" "VRS,VRX,VRI")]) +; vlvgb, vlvgh, vlvgf, vlvgg (define_insn "*vec_set_plus" [(set (match_operand:V 0 "register_operand" "=v") (unspec:V [(match_operand: 1 "general_operand" "d") @@ -366,6 +369,7 @@ UNSPEC_VEC_EXTRACT))] "TARGET_VX") +; vlgvb, vlgvh, vlgvf, vlgvg, vsteb, vsteh, vstef, vsteg (define_insn "*vec_extract" [(set (match_operand: 0 "nonimmediate_operand" "=d,R") (unspec: [(match_operand:V 1 "register_operand" "v,v") @@ -379,6 +383,7 @@ vste\t%v1,%0,%2" [(set_attr "op_type" "VRS,VRX")]) +; vlgvb, vlgvh, vlgvf, vlgvg (define_insn "*vec_extract_plus" [(set (match_operand: 0 "nonimmediate_operand" "=d") (unspec: [(match_operand:V 1 "register_operand" "v") @@ -399,6 +404,7 @@ }) ; Replicate from vector element +; vrepb, vreph, vrepf, vrepg (define_insn "*vec_splat" [(set (match_operand:V_HW 0 "register_operand" "=v") (vec_duplicate:V_HW @@ -410,6 +416,7 @@ "vrep\t%v0,%v1,%2" [(set_attr "op_type" "VRI")]) +; vlrepb, vlreph, vlrepf, vlrepg, vrepib, vrepih, vrepif, vrepig, vrepb, vreph, vrepf, vrepg (define_insn "*vec_splats" [(set (match_operand:V_HW 0 "register_operand" "=v,v,v,v") (vec_duplicate:V_HW (match_operand: 1 "general_operand" " R,K,v,d")))] @@ -692,6 +699,7 @@ }) ; Count leading zeros +; vclzb, vclzh, vclzf, vclzg (define_insn "clz2" [(set (match_operand:V 0 "register_operand" "=v") (clz:V (match_operand:V 1 "register_operand" "v")))] @@ -700,6 +708,7 @@ [(set_attr "op_type" "VRR")]) ; Count trailing zeros +; vctzb, vctzh, vctzf, vctzg (define_insn "ctz2" [(set (match_operand:V 0 "register_operand" "=v") (ctz:V (match_operand:V 1 "register_operand" "v")))] diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md index f2f430a8498..e53cca811ee 100644 --- a/gcc/config/s390/vx-builtins.md +++ b/gcc/config/s390/vx-builtins.md @@ -65,6 +65,7 @@ ; Vector gather element +; vgef, vgeg (define_insn "vec_gather_element" [(set (match_operand:V_HW_32_64 0 "register_operand" "=v") (unspec:V_HW_32_64 [(match_operand:V_HW_32_64 1 "register_operand" "0") @@ -167,6 +168,7 @@ ; vec_extract is also an RTL standard name -> vector.md +; vllezb, vllezh, vllezf, vllezg (define_insn "vec_insert_and_zero" [(set (match_operand:V_HW 0 "register_operand" "=v") (unspec:V_HW [(match_operand: 1 "memory_operand" "R")] @@ -187,6 +189,7 @@ ; FIXME: The following two patterns might using vec_merge. But what is ; the canonical form: (vec_select (vec_merge op0 op1)) or (vec_merge ; (vec_select op0) (vec_select op1) +; vmrhb, vmrhh, vmrhf, vmrhg (define_insn "vec_mergeh" [(set (match_operand:V_HW 0 "register_operand" "=v") (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v") @@ -196,6 +199,7 @@ "vmrh\t%v0,%1,%2" [(set_attr "op_type" "VRR")]) +; vmrlb, vmrlh, vmrlf, vmrlg (define_insn "vec_mergel" [(set (match_operand:V_HW 0 "register_operand" "=v") (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v") @@ -208,6 +212,7 @@ ; Vector pack +; vpkh, vpkf, vpkg (define_insn "vec_pack" [(set (match_operand: 0 "register_operand" "=v") (unspec: [(match_operand:VI_HW_HSD 1 "register_operand" "v") @@ -220,6 +225,7 @@ ; Vector pack saturate +; vpksh, vpksf, vpksg (define_insn "vec_packs" [(set (match_operand: 0 "register_operand" "=v") (unspec: [(match_operand:VI_HW_HSD 1 "register_operand" "v") @@ -249,6 +255,7 @@ operands[4] = gen_reg_rtx (SImode); }) +; vpksh, vpksf, vpksg (define_insn "*vec_packs_cc" [(set (reg:CCRAW CC_REGNUM) (unspec:CCRAW [(match_operand:VI_HW_HSD 1 "register_operand" "v") @@ -264,6 +271,7 @@ ; Vector pack logical saturate +; vpklsh, vpklsf, vpklsg (define_insn "vec_packsu" [(set (match_operand: 0 "register_operand" "=v") (unspec: [(match_operand:VI_HW_HSD 1 "register_operand" "v") @@ -322,6 +330,7 @@ operands[4] = gen_reg_rtx (SImode); }) +; vpklsh, vpklsf, vpklsg (define_insn "*vec_packsu_cc" [(set (reg:CCRAW CC_REGNUM) (unspec:CCRAW [(match_operand:VI_HW_HSD 1 "register_operand" "v") @@ -403,6 +412,7 @@ [(set_attr "op_type" "VRV")]) ; A 31 bit target address is generated from 64 bit elements +; vsceg (define_insn "vec_scatter_element_SI" [(set (mem: (plus:SI (subreg:SI @@ -417,6 +427,7 @@ [(set_attr "op_type" "VRV")]) ; Element size and target address size is the same +; vscef, vsceg (define_insn "vec_scatter_element_" [(set (mem: (plus: (unspec: @@ -482,6 +493,7 @@ ; Vector sign extend to doubleword ; Sign extend of right most vector element to respective double-word +; vsegb, vsegh, vsegf (define_insn "vec_extend" [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")] @@ -551,6 +563,7 @@ ; Vector add compute carry +; vaccb, vacch, vaccf, vaccg, vaccq (define_insn "vacc_" [(set (match_operand:VIT_HW 0 "register_operand" "=v") (unspec:VIT_HW [(match_operand:VIT_HW 1 "register_operand" "%v") @@ -638,6 +651,7 @@ ; Vector average +; vavgb, vavgh, vavgf, vavgg (define_insn "vec_avg" [(set (match_operand:VI_HW 0 "register_operand" "=v") (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "%v") @@ -649,6 +663,7 @@ ; Vector average logical +; vavglb, vavglh, vavglf, vavglg (define_insn "vec_avgu" [(set (match_operand:VI_HW 0 "register_operand" "=v") (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "%v") @@ -787,6 +802,7 @@ ; Vector Galois field multiply sum +; vgfmb, vgfmh, vgfmf (define_insn "vec_gfmsum" [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") @@ -805,6 +821,7 @@ "vgfmg\t%v0,%v1,%v2" [(set_attr "op_type" "VRR")]) +; vgfmab, vgfmah, vgfmaf (define_insn "vec_gfmsum_accum" [(set (match_operand: 0 "register_operand" "=v") (unspec: [(match_operand:VI_HW_QHS 1 "register_operand" "v") @@ -1115,6 +1132,7 @@ ; Vector subtract compute borrow indication +; vscbib, vscbih, vscbif, vscbig, vscbiq (define_insn "vscbi_" [(set (match_operand:VIT_HW 0 "register_operand" "=v") (unspec:VIT_HW [(match_operand:VIT_HW 1 "register_operand" "v") -- 2.30.2