From 50f1fb37074d0771c1ae06a0c4f97cb03acd1473 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 25 Dec 2020 00:17:32 +0000 Subject: [PATCH] --- openpower/sv/overview.mdwn | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn index ecb6cf07d..9fa50daca 100644 --- a/openpower/sv/overview.mdwn +++ b/openpower/sv/overview.mdwn @@ -249,4 +249,5 @@ Here's the interesting part: given the fact that SV is a "context" extension, th It also turns out that by using a single bit set in the source or destination, *all* the sequential ordered standard patterns of Vector ISAs are provided: VSPLAT, VSELECT, VINSERT, VCOMPRESS, VEXPAND. -The only one missing from the list here, because it is non-sequential, is VGATHER: moving registers by specifying a vector of register indices (`regs[rd] = regs[regs[rs]]` in a loop). +The only one missing from the list here, because it is non-sequential, is VGATHER: moving registers by specifying a vector of register indices (`regs[rd] = regs[regs[rs]]` in a loop). This one is tricky because it typically does not exist in standard scalar ISAs. If it did it would be called [[sv/mv.x]] + -- 2.30.2