From 5134eb95c9699e7d2c99cc356b7c242b884a280f Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 10 Dec 2020 01:52:08 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64/discussion.mdwn | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn index 633719bba..71c81f411 100644 --- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn +++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn @@ -13,10 +13,19 @@ http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001434.html ## twin predication +something like: + | 0 1 | 2 3 | 4 5 | 6 | 7 9 | 10 12 | 13 18 | | ----- | --- | --- | ---- | ---- | ----- | ----- | | subvl | sew | dew | ptyp | psrc | pdst | vspec | +* subvl - 1 to 4 scalar / vec2 / vec3 / vec4 +* sew / dew - DEFAULT / 8 / 16 /32 element width +* ptyp - predication INT / CR +* psrc / pdst - predicate mask selector and inversion +* vspec - 3 bit src / dest scalar-vector extension + + # Notes about Swizzle Basically, there isn't enough room to try to fit two src src1/2 swizzle, and SV, even into 64 bit (actually 24) without severely compromising on the number of bits allocated to either swizzle, or SV, or both. -- 2.30.2