From 514a91d33f82b80e8ddaaf9b214f9caf33dbbfea Mon Sep 17 00:00:00 2001 From: Sandipan Das Date: Thu, 7 Jun 2018 03:11:17 +0530 Subject: [PATCH] arch-power: Add fixed-point byte-reversed load and store instructions This adds the following load and store instructions: * Load Halfword Byte-Reverse Indexed (lhbrx) * Load Word Byte-Reverse Indexed (lwbrx) * Load Doubleword Byte-Reverse Indexed (ldbrx) * Store Halfword Byte-Reverse Indexed (sthbrx) * Store Word Byte-Reverse Indexed (stwbrx) * Store Doubleword Byte-Reverse Indexed (stdbrx) Change-Id: I9f211bb4e3007ca09002a9ba4e5afb4b2e67cddd Signed-off-by: Sandipan Das --- src/arch/power/isa/decoder.isa | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa index 8ef8ead20..20d1f741b 100644 --- a/src/arch/power/isa/decoder.isa +++ b/src/arch/power/isa/decoder.isa @@ -266,10 +266,13 @@ decode PO default Unknown::unknown() { 87: lbzx({{ Rt = Mem_ub; }}); 279: lhzx({{ Rt = Mem_uh; }}); 343: lhax({{ Rt = Mem_sh; }}); + 790: lhbrx({{ Rt = swap_byte(Mem_uh); }}); 23: lwzx({{ Rt = Mem_uw; }}); 341: lwax({{ Rt = Mem_sw; }}); 20: lwarx({{ Rt = Mem_uw; Rsv = 1; RsvLen = 4; RsvAddr = EA; }}); + 534: lwbrx({{ Rt = swap_byte(Mem_uw); }}); 21: ldx({{ Rt = Mem; }}); + 532: ldbrx({{ Rt = swap_byte(Mem); }}); 535: lfsx({{ Ft_sf = Mem_sf; }}); 599: lfdx({{ Ft = Mem_df; }}); 855: lfiwax({{ Ft_uw = Mem; }}); @@ -289,6 +292,7 @@ decode PO default Unknown::unknown() { format StoreIndexOp { 215: stbx({{ Mem_ub = Rs_ub; }}); 407: sthx({{ Mem_uh = Rs_uh; }}); + 918: sthbrx({{ Mem_uh = swap_byte(Rs_uh); }}); 151: stwx({{ Mem_uw = Rs_uw; }}); 150: stwcx({{ bool store_performed = false; @@ -306,7 +310,9 @@ decode PO default Unknown::unknown() { CR = cr; Rsv = 0; }}); + 662: stwbrx({{ Mem_uw = swap_byte(Rs_uw); }}); 149: stdx({{ Mem = Rs }}); + 660: stdbrx({{ Mem = swap_byte(Rs); }}); } format StoreIndexUpdateOp { -- 2.30.2