From 515d476d00384f2efd5082bbee79d0398ef445c3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 15 May 2020 12:28:15 +0100 Subject: [PATCH] add some more tests to countzero --- src/soc/countzero/test/test_countzero.py | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/src/soc/countzero/test/test_countzero.py b/src/soc/countzero/test/test_countzero.py index 538db15c..e4ca3519 100644 --- a/src/soc/countzero/test/test_countzero.py +++ b/src/soc/countzero/test/test_countzero.py @@ -55,6 +55,29 @@ class ZeroCounterTestCase(FHDLTestCase): result = yield dut.result_o assert result == 59, "result %d" % result + yield dut.is_32bit_i.eq(1) + yield Delay(1e-6) + result = yield dut.result_o + assert result == 27, "result %d" % result + + yield dut.rs_i.eq(0b1100000100000000) + yield dut.is_32bit_i.eq(0) + yield dut.count_right_i.eq(0) + yield Delay(1e-6) + result = yield dut.result_o + assert result == 8, "result %d" % result + + yield dut.count_right_i.eq(1) + yield Delay(1e-6) + result = yield dut.result_o + assert result == 55, "result %d" % result + + yield dut.is_32bit_i.eq(1) + yield Delay(1e-6) + result = yield dut.result_o + assert result == 23, "result %d" % result + + sim.add_process(process) # or sim.add_sync_process(process), see below # run test and write vcd -- 2.30.2