From 51df413634b4dac2fc5e538a13c8f8624903c59e Mon Sep 17 00:00:00 2001 From: Kewen Lin Date: Sun, 29 Sep 2019 05:08:14 +0000 Subject: [PATCH] This patch is to add the support for float from/to long conversion vectorization on port rs6000. gcc/ChangeLog 2019-09-29 Kewen Lin * config/rs6000/vsx.md (vec_pack[su]_float_v2di): New define_expand. (vec_unpack_[su]fix_trunc_hi_v4sf): Likewise. (vec_unpack_[su]fix_trunc_lo_v4sf): Likewise. gcc/testsuite/ChangeLog 2019-09-29 Kewen Lin * gcc.target/powerpc/conv-vectorize-1.c: New test. * gcc.target/powerpc/conv-vectorize-2.c: New test. From-SVN: r276266 --- gcc/ChangeLog | 6 +++ gcc/config/rs6000/vsx.md | 45 +++++++++++++++++++ gcc/testsuite/ChangeLog | 5 +++ .../gcc.target/powerpc/conv-vectorize-1.c | 37 +++++++++++++++ .../gcc.target/powerpc/conv-vectorize-2.c | 37 +++++++++++++++ 5 files changed, 130 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/conv-vectorize-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/conv-vectorize-2.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 88fed01cd52..9714e98df9f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2019-09-29 Kewen Lin + + * config/rs6000/vsx.md (vec_pack[su]_float_v2di): New define_expand. + (vec_unpack_[su]fix_trunc_hi_v4sf): Likewise. + (vec_unpack_[su]fix_trunc_lo_v4sf): Likewise. + 2019-09-28 Iain Sandoe * config/darwin.c (gen_macho_high): Amend to include the mode diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 91f5feddcf3..3cc1277aaee 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -5544,3 +5544,48 @@ operands[SFBOOL_TMP_VSX_DI] = gen_rtx_REG (DImode, regno_tmp_vsx); operands[SFBOOL_MTVSR_D_V4SF] = gen_rtx_REG (V4SFmode, regno_mtvsr_d); }) + +;; Support signed/unsigned long long to float conversion vectorization. +;; Note that any_float (pc) here is just for code attribute . +(define_expand "vec_pack_float_v2di" + [(match_operand:V4SF 0 "vfloat_operand") + (match_operand:V2DI 1 "vint_operand") + (match_operand:V2DI 2 "vint_operand") + (any_float (pc))] + "TARGET_VSX" +{ + rtx r1 = gen_reg_rtx (V4SFmode); + rtx r2 = gen_reg_rtx (V4SFmode); + emit_insn (gen_vsx_xvcvxdsp (r1, operands[1])); + emit_insn (gen_vsx_xvcvxdsp (r2, operands[2])); + rs6000_expand_extract_even (operands[0], r1, r2); + DONE; +}) + +;; Support float to signed/unsigned long long conversion vectorization. +;; Note that any_fix (pc) here is just for code attribute . +(define_expand "vec_unpack_fix_trunc_hi_v4sf" + [(match_operand:V2DI 0 "vint_operand") + (match_operand:V4SF 1 "vfloat_operand") + (any_fix (pc))] + "TARGET_VSX" +{ + rtx reg = gen_reg_rtx (V4SFmode); + rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN); + emit_insn (gen_vsx_xvcvspxds (operands[0], reg)); + DONE; +}) + +;; Note that any_fix (pc) here is just for code attribute . +(define_expand "vec_unpack_fix_trunc_lo_v4sf" + [(match_operand:V2DI 0 "vint_operand") + (match_operand:V4SF 1 "vfloat_operand") + (any_fix (pc))] + "TARGET_VSX" +{ + rtx reg = gen_reg_rtx (V4SFmode); + rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN); + emit_insn (gen_vsx_xvcvspxds (operands[0], reg)); + DONE; +}) + diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5592df3e745..d0d2cb084c5 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2019-09-29 Kewen Lin + + * gcc.target/powerpc/conv-vectorize-1.c: New test. + * gcc.target/powerpc/conv-vectorize-2.c: New test. + 2019-09-28 Steven G. Kargl PR fortran/91802 diff --git a/gcc/testsuite/gcc.target/powerpc/conv-vectorize-1.c b/gcc/testsuite/gcc.target/powerpc/conv-vectorize-1.c new file mode 100644 index 00000000000..d96db146864 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/conv-vectorize-1.c @@ -0,0 +1,37 @@ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -ftree-vectorize -mvsx" } */ + +/* Test vectorizer can exploit vector conversion instructions to convert + unsigned/signed long long to float. */ + +#include + +#define SIZE 32 +#define ALIGN 16 + +float sflt_array[SIZE] __attribute__ ((__aligned__ (ALIGN))); +float uflt_array[SIZE] __attribute__ ((__aligned__ (ALIGN))); + +unsigned long long ulong_array[SIZE] __attribute__ ((__aligned__ (ALIGN))); +signed long long slong_array[SIZE] __attribute__ ((__aligned__ (ALIGN))); + +void +convert_slong_to_float (void) +{ + size_t i; + + for (i = 0; i < SIZE; i++) + sflt_array[i] = (float) slong_array[i]; +} + +void +convert_ulong_to_float (void) +{ + size_t i; + + for (i = 0; i < SIZE; i++) + uflt_array[i] = (float) ulong_array[i]; +} + +/* { dg-final { scan-assembler {\mxvcvsxdsp\M} } } */ +/* { dg-final { scan-assembler {\mxvcvuxdsp\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/conv-vectorize-2.c b/gcc/testsuite/gcc.target/powerpc/conv-vectorize-2.c new file mode 100644 index 00000000000..5dd5deabdd3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/conv-vectorize-2.c @@ -0,0 +1,37 @@ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -ftree-vectorize -mvsx" } */ + +/* Test vectorizer can exploit vector conversion instructions to convert + float to unsigned/signed long long. */ + +#include + +#define SIZE 32 +#define ALIGN 16 + +float sflt_array[SIZE] __attribute__ ((__aligned__ (ALIGN))); +float uflt_array[SIZE] __attribute__ ((__aligned__ (ALIGN))); + +unsigned long long ulong_array[SIZE] __attribute__ ((__aligned__ (ALIGN))); +signed long long slong_array[SIZE] __attribute__ ((__aligned__ (ALIGN))); + +void +convert_float_to_slong (void) +{ + size_t i; + + for (i = 0; i < SIZE; i++) + slong_array[i] = (signed long long) sflt_array[i]; +} + +void +convert_float_to_ulong (void) +{ + size_t i; + + for (i = 0; i < SIZE; i++) + ulong_array[i] = (unsigned long long) uflt_array[i]; +} + +/* { dg-final { scan-assembler {\mxvcvspsxds\M} } } */ +/* { dg-final { scan-assembler {\mxvcvspuxds\M} } } */ -- 2.30.2