From 51e2e6ecd076178584910f231dbace7656eb23cd Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 18 Nov 2012 16:32:51 +0100 Subject: [PATCH] fhdl/verilog: remove empty cases --- migen/fhdl/verilog.py | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index 8373e012..f41dbf05 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -81,17 +81,20 @@ def _printnode(ns, at, level, node): r += "\t"*level + "end\n" return r elif isinstance(node, Case): - r = "\t"*level + "case (" + _printexpr(ns, node.test) + ")\n" - for case in node.cases: - r += "\t"*(level + 1) + _printexpr(ns, case[0]) + ": begin\n" - r += _printnode(ns, at, level + 2, case[1]) - r += "\t"*(level + 1) + "end\n" - if node.default: - r += "\t"*(level + 1) + "default: begin\n" - r += _printnode(ns, at, level + 2, node.default) - r += "\t"*(level + 1) + "end\n" - r += "\t"*level + "endcase\n" - return r + if node.cases or node.default: + r = "\t"*level + "case (" + _printexpr(ns, node.test) + ")\n" + for case in node.cases: + r += "\t"*(level + 1) + _printexpr(ns, case[0]) + ": begin\n" + r += _printnode(ns, at, level + 2, case[1]) + r += "\t"*(level + 1) + "end\n" + if node.default: + r += "\t"*(level + 1) + "default: begin\n" + r += _printnode(ns, at, level + 2, node.default) + r += "\t"*(level + 1) + "end\n" + r += "\t"*level + "endcase\n" + return r + else: + return "" else: raise TypeError -- 2.30.2