From 51e654f4aa5b4a6c1df58776715fc017966f18b9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 2 May 2019 15:41:44 +0100 Subject: [PATCH] tidy imports --- src/ieee754/add/test_fsm_experiment.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieee754/add/test_fsm_experiment.py b/src/ieee754/add/test_fsm_experiment.py index 204a7d18..cfc401e8 100644 --- a/src/ieee754/add/test_fsm_experiment.py +++ b/src/ieee754/add/test_fsm_experiment.py @@ -6,8 +6,8 @@ from nmigen import Module, Signal, Const, Cat, Elaboratable from nmigen.cli import main, verilog, rtlil from nmigen.compat.sim import run_simulation - -from ieee754.fpcommon.fpbase import FPNumIn, FPNumOut, FPOpIn, FPOpOut, FPBase, FPState +from ieee754.fpcommon.fpbase import (FPNumIn, FPNumOut, FPOpIn, + FPOpOut, FPBase) from nmutil.nmoperator import eq from nmutil.singlepipe import SimpleHandshake, ControlBase from test_buf_pipe import data_chain2, Test5 -- 2.30.2