From 51eb8bc7436f6283c2f4faa170ce30e1add71a9d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 4 Jun 2020 18:27:03 +0100 Subject: [PATCH] add extra argument (not used) to regfile.py --- src/soc/regfile/regfile.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/soc/regfile/regfile.py b/src/soc/regfile/regfile.py index 918f8ea8..3e3c4538 100644 --- a/src/soc/regfile/regfile.py +++ b/src/soc/regfile/regfile.py @@ -225,6 +225,7 @@ class RegFile(Elaboratable): else: yield r + def regfile_sim(dut, rp, wp): yield wp.waddr.eq(1) yield wp.data_i.eq(2) @@ -259,7 +260,8 @@ def regfile_sim(dut, rp, wp): data = yield rp.data_o print (data) -def regfile_array_sim(dut, rp1, rp2, wp): +def regfile_array_sim(dut, rp1, rp2, wp, wp2): + print ("regfile_array_sim") yield wp.data_i.eq(2) yield wp.wen.eq(1<<1) yield @@ -310,13 +312,14 @@ def test_regfile(): rp1 = dut.read_port("read1") rp2 = dut.read_port("read2") wp = dut.write_port("write") + wp2 = dut.write_port("write2") ports=dut.ports() print ("ports", ports) vl = rtlil.convert(dut, ports=ports) with open("test_regfile_array.il", "w") as f: f.write(vl) - run_simulation(dut, regfile_array_sim(dut, rp1, rp2, wp), + run_simulation(dut, regfile_array_sim(dut, rp1, rp2, wp, wp2), vcd_name='test_regfile_array.vcd') if __name__ == '__main__': -- 2.30.2