From 523d72071960ddca69139b9fd96ad8c8ce79ac0e Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Wed, 27 Apr 2016 19:52:58 +0000 Subject: [PATCH] [AArch64] Replace insn to zero up SIMD registers gcc/ * config/aarch64/aarch64.md (*movhf_aarch64): Add "movi %0, #0" to zero up register and remove the "fp" attributes. (*movsf_aarch64): Add "movi %0, #0" to zero up register and add the "simd" attributes. (*movdf_aarch64): Likewise. (*movtf_aarch64): Remove the "fp" attributes. * testsuite/gcc.target/aarch64/fmovf-zero-reg.c: Update accordingly. * testsuite/gcc.target/aarch64/fmovd-zero-reg.c: Likewise. From-SVN: r235532 --- gcc/ChangeLog | 12 +++++++ gcc/config/aarch64/aarch64.md | 31 ++++++++++--------- .../gcc.target/aarch64/fmovd-zero-reg.c | 2 +- .../gcc.target/aarch64/fmovf-zero-reg.c | 2 +- 4 files changed, 31 insertions(+), 16 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a5fea2a44a8..4f35001da1d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2016-04-26 Evandro Menezes + + * config/aarch64/aarch64.md + (*movhf_aarch64): Add "movi %0, #0" to zero up register and + remove the "fp" attributes. + (*movsf_aarch64): Add "movi %0, #0" to zero up register and + add the "simd" attributes. + (*movdf_aarch64): Likewise. + (*movtf_aarch64): Remove the "fp" attributes. + * testsuite/gcc.target/aarch64/fmovf-zero-reg.c: Update accordingly. + * testsuite/gcc.target/aarch64/fmovd-zero-reg.c: Likewise. + 2016-04-27 David Malcolm * emit-rtl.c (maybe_set_first_label_num): Strengthen param from diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index f423284ea01..9b282f13388 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1178,11 +1178,12 @@ ) (define_insn "*movhf_aarch64" - [(set (match_operand:HF 0 "nonimmediate_operand" "=w, ?r,w,w,m,r,m ,r") - (match_operand:HF 1 "general_operand" "?rY, w,w,m,w,m,rY,r"))] + [(set (match_operand:HF 0 "nonimmediate_operand" "=w,w ,?r,w,w,m,r,m ,r") + (match_operand:HF 1 "general_operand" "Y ,?rY, w,w,m,w,m,rY,r"))] "TARGET_FLOAT && (register_operand (operands[0], HFmode) || aarch64_reg_or_fp_zero (operands[1], HFmode))" "@ + movi\\t%0.4h, #0 mov\\t%0.h[0], %w1 umov\\t%w0, %1.h[0] mov\\t%0.h[0], %1.h[0] @@ -1191,18 +1192,18 @@ ldrh\\t%w0, %1 strh\\t%w1, %0 mov\\t%w0, %w1" - [(set_attr "type" "neon_from_gp,neon_to_gp,neon_move,\ + [(set_attr "type" "neon_move,neon_from_gp,neon_to_gp,neon_move,\ f_loads,f_stores,load1,store1,mov_reg") - (set_attr "simd" "yes,yes,yes,*,*,*,*,*") - (set_attr "fp" "*,*,*,yes,yes,*,*,*")] + (set_attr "simd" "yes,yes,yes,yes,*,*,*,*,*")] ) (define_insn "*movsf_aarch64" - [(set (match_operand:SF 0 "nonimmediate_operand" "=w, ?r,w,w ,w,m,r,m ,r") - (match_operand:SF 1 "general_operand" "?rY, w,w,Ufc,m,w,m,rY,r"))] + [(set (match_operand:SF 0 "nonimmediate_operand" "=w,w ,?r,w,w ,w,m,r,m ,r") + (match_operand:SF 1 "general_operand" "Y ,?rY, w,w,Ufc,m,w,m,rY,r"))] "TARGET_FLOAT && (register_operand (operands[0], SFmode) || aarch64_reg_or_fp_zero (operands[1], SFmode))" "@ + movi\\t%0.2s, #0 fmov\\t%s0, %w1 fmov\\t%w0, %s1 fmov\\t%s0, %s1 @@ -1212,16 +1213,18 @@ ldr\\t%w0, %1 str\\t%w1, %0 mov\\t%w0, %w1" - [(set_attr "type" "f_mcr,f_mrc,fmov,fconsts,\ - f_loads,f_stores,load1,store1,mov_reg")] + [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconsts,\ + f_loads,f_stores,load1,store1,mov_reg") + (set_attr "simd" "yes,*,*,*,*,*,*,*,*,*")] ) (define_insn "*movdf_aarch64" - [(set (match_operand:DF 0 "nonimmediate_operand" "=w, ?r,w,w ,w,m,r,m ,r") - (match_operand:DF 1 "general_operand" "?rY, w,w,Ufc,m,w,m,rY,r"))] + [(set (match_operand:DF 0 "nonimmediate_operand" "=w,w ,?r,w,w ,w,m,r,m ,r") + (match_operand:DF 1 "general_operand" "Y ,?rY, w,w,Ufc,m,w,m,rY,r"))] "TARGET_FLOAT && (register_operand (operands[0], DFmode) || aarch64_reg_or_fp_zero (operands[1], DFmode))" "@ + movi\\t%d0, #0 fmov\\t%d0, %x1 fmov\\t%x0, %d1 fmov\\t%d0, %d1 @@ -1231,8 +1234,9 @@ ldr\\t%x0, %1 str\\t%x1, %0 mov\\t%x0, %x1" - [(set_attr "type" "f_mcr,f_mrc,fmov,fconstd,\ - f_loadd,f_stored,load1,store1,mov_reg")] + [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconstd,\ + f_loadd,f_stored,load1,store1,mov_reg") + (set_attr "simd" "yes,*,*,*,*,*,*,*,*,*")] ) (define_insn "*movtf_aarch64" @@ -1257,7 +1261,6 @@ [(set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,neon_move_q,f_mcr,\ f_loadd,f_stored,load2,store2,store2") (set_attr "length" "4,8,8,8,4,4,4,4,4,4,4") - (set_attr "fp" "*,*,yes,yes,*,yes,yes,yes,*,*,*") (set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*,*")] ) diff --git a/gcc/testsuite/gcc.target/aarch64/fmovd-zero-reg.c b/gcc/testsuite/gcc.target/aarch64/fmovd-zero-reg.c index 0a3e5940297..c6c94148931 100644 --- a/gcc/testsuite/gcc.target/aarch64/fmovd-zero-reg.c +++ b/gcc/testsuite/gcc.target/aarch64/fmovd-zero-reg.c @@ -8,4 +8,4 @@ foo (void) bar (0.0); } -/* { dg-final { scan-assembler "fmov\\td0, xzr" } } */ +/* { dg-final { scan-assembler "movi\\td0, #0" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/fmovf-zero-reg.c b/gcc/testsuite/gcc.target/aarch64/fmovf-zero-reg.c index 4213450d6e5..071dfa9da1d 100644 --- a/gcc/testsuite/gcc.target/aarch64/fmovf-zero-reg.c +++ b/gcc/testsuite/gcc.target/aarch64/fmovf-zero-reg.c @@ -8,4 +8,4 @@ foo (void) bar (0.0); } -/* { dg-final { scan-assembler "fmov\\ts0, wzr" } } */ +/* { dg-final { scan-assembler "movi\\tv0\.2s, #0" } } */ -- 2.30.2