From 5257dbc0a275212951d0930277205f45506e7e33 Mon Sep 17 00:00:00 2001 From: whitequark Date: Fri, 14 Dec 2018 16:07:25 +0000 Subject: [PATCH] fhdl.ast: fix Switch with constant test. --- nmigen/fhdl/ast.py | 4 ++-- nmigen/test/test_fhdl_dsl.py | 14 ++++++++++++++ 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/nmigen/fhdl/ast.py b/nmigen/fhdl/ast.py index 3455b38..77a7ff2 100644 --- a/nmigen/fhdl/ast.py +++ b/nmigen/fhdl/ast.py @@ -678,9 +678,9 @@ class Switch(Statement): self.cases = OrderedDict() for key, stmts in cases.items(): if isinstance(key, (bool, int)): - key = "{:0{}b}".format(key, len(test)) + key = "{:0{}b}".format(key, len(self.test)) elif isinstance(key, str): - assert len(key) == len(test) + assert len(key) == len(self.test) else: raise TypeError if not isinstance(stmts, Iterable): diff --git a/nmigen/test/test_fhdl_dsl.py b/nmigen/test/test_fhdl_dsl.py index e28ced6..f8b109e 100644 --- a/nmigen/test/test_fhdl_dsl.py +++ b/nmigen/test/test_fhdl_dsl.py @@ -263,6 +263,20 @@ class DSLTestCase(FHDLTestCase): ) """) + def test_Switch_const_test(self): + m = Module() + with m.Switch(1): + with m.Case(1): + m.d.comb += self.c1.eq(1) + m._flush() + self.assertRepr(m._statements, """ + ( + (switch (const 1'd1) + (case 1 (eq (sig c1) (const 1'd1))) + ) + ) + """) + def test_Case_width_wrong(self): m = Module() with m.Switch(self.w1): -- 2.30.2