From 52583ecff82eb9dc78e10b7bfd33c1be3d4dcc67 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 4 Oct 2019 13:33:27 -0700
Subject: [PATCH] Revert "Fix TODOs"

This reverts commit 8674a6c68d563908014d16671567459499c6dc99.
---
 passes/pmgen/xilinx_dsp.pmg      | 15 +++++++++++++++
 passes/pmgen/xilinx_dsp_CREG.pmg |  5 +++++
 2 files changed, 20 insertions(+)

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 3523db3a4..8a2c2caf5 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -103,6 +103,11 @@ code sigA sigB sigC sigD sigM clock
 	}
 	else
 		sigM = P;
+	// TODO: Check if necessary
+	// This sigM could have no users if downstream $add
+	//   is narrower than $mul result, for example
+	if (sigM.empty())
+		reject;
 
 	clock = port(dsp, \CLK, SigBit());
 endcode
@@ -154,6 +159,16 @@ match preAdd
 	optional
 endmatch
 
+code sigA sigD
+	// TODO: Check if this is necessary?
+	if (preAdd) {
+		sigA = port(preAdd, \A);
+		sigD = port(preAdd, \B);
+		if (GetSize(sigA) < GetSize(sigD))
+			std::swap(sigA, sigD);
+	}
+endcode
+
 // (4) If pre-adder was present, find match 'A' input for A2REG
 //     If pre-adder was not present, move ADREG to A2REG
 //     Then match 'A' input for A1REG
diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg
index 3d911b478..b87a686a1 100644
--- a/passes/pmgen/xilinx_dsp_CREG.pmg
+++ b/passes/pmgen/xilinx_dsp_CREG.pmg
@@ -79,6 +79,11 @@ endcode
 //     (attached to at most two $mux cells that implement clock-enable or
 //      reset functionality, using the in_dffe subpattern)
 code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock
+	// TODO: Any downside to allowing this?
+	// If this DSP implements an accumulator, do not attempt to match
+	if (sigC == sigP)
+		reject;
+
 	argQ = sigC;
 	subpattern(in_dffe);
 	if (dff) {
-- 
2.30.2