From 52873c1fb11279e5a8c2180a171e21481ee14900 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 5 May 2022 23:57:17 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index e2a314c32..cd49217b5 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -320,8 +320,20 @@ ISAs have quite comprehensive arithmetic and logical operations on Predicate Masks, and if CR Fields were the only predicates in SVP64 it would put pressure on to start adding the exact same arithmetic and logical operations that already exist in the Integer opcodes. - Instead of taking that route the decision was made to allow *both* Integer *and* CR Fields to be Predicate Masks, and to create Draft instructions that provide better transfer capability between CR Fields and Integer Register files. + +Beyond that, further extensions to the Power ISA become much more +domain-specific, such as adding bitmanipulation for Audio, Video +and Cryptographic use-cases, or adding Transcendentals (`LOG1P`, +`ATAN2` etc) for 3D and other GPU workloads. The huge advantage here +of the SVP64 "Prefix" approach is that anything added to the Scalar ISA +*automatically* is inherently added to the Vector one as well, and +because these GPU and Video opcodes have been added to the CPU ISA, +Software Driver development and debugging is dramatically simplified. + +Which brings us to the next important question: how is any of these +CPU-centric Vector-centric improvements relevant to power efficiency +and making more effective use of resources? -- 2.30.2