From 528e55c1c721c98d3c0e7e41405e0790f7c106f8 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Sat, 30 Oct 2021 11:15:17 +0200 Subject: [PATCH] loadstore.py: add debug output for dcbz --- src/soc/fu/ldst/loadstore.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py index 7400c0ae..22acd797 100644 --- a/src/soc/fu/ldst/loadstore.py +++ b/src/soc/fu/ldst/loadstore.py @@ -128,6 +128,8 @@ class LoadStore1(PortInterfaceBase): m.d.comb += self.req.align_intr.eq(misalign) m.d.comb += self.req.dcbz.eq(is_dcbz) + m.d.comb += Display("set_wr_addr %i dcbz %i",addr,is_dcbz) + # option to disable the cache entirely for write if self.disable_cache: m.d.comb += self.req.nc.eq(1) -- 2.30.2