From 5291fe3cd14f2861fad43303a10550e71dc14182 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Tue, 12 Jan 2021 13:57:23 +0000 Subject: [PATCH] aarch64: Add support for bfloat16 in gdb. This patch adds support for bfloat16 in AArch64 gdb. Also adds the field "bf" to vector registers h0-h31. Also adds the vector "bf" to h field in vector registers v0-v31. The following is how the vector register h and v looks like. Before this patch: (gdb) p $h0 $1 = {f = 0, u = 0, s = 0} (gdb) p/x $h0 $2 = {f = 0x0, u = 0x0, s = 0x0} (gdb) p $v0.h $3 = {f = {0, 0, 0, 0, 0, 0, 0, 0}, u = {0, 0, 0, 0, 0, 0, 0, 0}, s = {0, 0, 0, 0, 0, 0, 0, 0}} (gdb) p/x $v0.h $4 = {f = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, s = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}} After this patch: (gdb) p $h0 $1 = {bf = 0, f = 0, u = 0, s = 0} (gdb) p/x $h0 $2 = {bf = 0x0, f = 0x0, u = 0x0, s = 0x0} (gdb) p $v0.h $3 = {bf = {0, 0, 0, 0, 0, 0, 0, 0}, f = {0, 0, 0, 0, 0, 0, 0, 0}, u = {0, 0, 0, 0, 0, 0, 0, 0}, s = {0, 0, 0, 0, 0, 0, 0, 0}} (gdb) p/x $v0.h $4 = {bf = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, f = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, s = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}} gdb/ChangeLog: 2021-01-12 Srinath Parvathaneni * aarch64-tdep.c (aarch64_vnh_type): Add "bf" field in h registers. (aarch64_vnv_type): Add "bf" type in h field of v registers. * features/aarch64-fpu.c (create_feature_aarch64_fpu): Regenerated. * features/aarch64-fpu.xml: Add bfloat16 type. gdb/testsuite/ChangeLog: 2021-01-12 Srinath Parvathaneni * gdb.arch/aarch64-fp.exp: Modify to test bfloat16 support. --- gdb/ChangeLog | 7 +++++++ gdb/aarch64-tdep.c | 5 +++++ gdb/features/aarch64-fpu.c | 5 +++++ gdb/features/aarch64-fpu.xml | 2 ++ gdb/testsuite/ChangeLog | 4 ++++ gdb/testsuite/gdb.arch/aarch64-fp.exp | 25 +++++++++++++++++++++++++ 6 files changed, 48 insertions(+) diff --git a/gdb/ChangeLog b/gdb/ChangeLog index d4a1b98aaca..27d5b96f141 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,10 @@ +2021-01-12 Srinath Parvathaneni + + * aarch64-tdep.c (aarch64_vnh_type): Add "bf" field in h registers. + (aarch64_vnv_type): Add "bf" type in h field of v registers. + * features/aarch64-fpu.c (create_feature_aarch64_fpu): Regenerated. + * features/aarch64-fpu.xml: Add bfloat16 type. + 2021-01-12 Andrew Burgess * expprint.c (dump_subexp_body_standard): Handle OP_BOOL. diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index 5d1d979cd37..7099f180101 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -2040,6 +2040,9 @@ aarch64_vnh_type (struct gdbarch *gdbarch) t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh", TYPE_CODE_UNION); + elem = builtin_type (gdbarch)->builtin_bfloat16; + append_composite_type_field (t, "bf", elem); + elem = builtin_type (gdbarch)->builtin_half; append_composite_type_field (t, "f", elem); @@ -2121,6 +2124,8 @@ aarch64_vnv_type (struct gdbarch *gdbarch) sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh", TYPE_CODE_UNION); + append_composite_type_field (sub, "bf", + init_vector_type (bt->builtin_bfloat16, 8)); append_composite_type_field (sub, "f", init_vector_type (bt->builtin_half, 8)); append_composite_type_field (sub, "u", diff --git a/gdb/features/aarch64-fpu.c b/gdb/features/aarch64-fpu.c index 5b636a5f4d2..a80b7d4c1b8 100644 --- a/gdb/features/aarch64-fpu.c +++ b/gdb/features/aarch64-fpu.c @@ -37,6 +37,9 @@ create_feature_aarch64_fpu (struct target_desc *result, long regnum) element_type = tdesc_named_type (feature, "int16"); tdesc_create_vector (feature, "v8i", element_type, 8); + element_type = tdesc_named_type (feature, "bfloat16"); + tdesc_create_vector (feature, "v8bf16", element_type, 8); + element_type = tdesc_named_type (feature, "uint8"); tdesc_create_vector (feature, "v16u", element_type, 16); @@ -68,6 +71,8 @@ create_feature_aarch64_fpu (struct target_desc *result, long regnum) tdesc_add_field (type_with_fields, "s", field_type); type_with_fields = tdesc_create_union (feature, "vnh"); + field_type = tdesc_named_type (feature, "v8bf16"); + tdesc_add_field (type_with_fields, "bf", field_type); field_type = tdesc_named_type (feature, "v8f"); tdesc_add_field (type_with_fields, "f", field_type); field_type = tdesc_named_type (feature, "v8u"); diff --git a/gdb/features/aarch64-fpu.xml b/gdb/features/aarch64-fpu.xml index 14b31373734..2235d072a09 100644 --- a/gdb/features/aarch64-fpu.xml +++ b/gdb/features/aarch64-fpu.xml @@ -17,6 +17,7 @@ + @@ -32,6 +33,7 @@ + diff --git a/gdb/testsuite/ChangeLog b/gdb/testsuite/ChangeLog index 7c24f66b914..eb42dedc18e 100644 --- a/gdb/testsuite/ChangeLog +++ b/gdb/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2021-01-12 Srinath Parvathaneni + + * gdb.arch/aarch64-fp.exp: Modify to test bfloat16 support. + 2021-01-12 Tom de Vries * gdb.base/disasm-optim.exp: Require is_amd64_regs_target. diff --git a/gdb/testsuite/gdb.arch/aarch64-fp.exp b/gdb/testsuite/gdb.arch/aarch64-fp.exp index 8d06a3f5201..4fb8e343c49 100644 --- a/gdb/testsuite/gdb.arch/aarch64-fp.exp +++ b/gdb/testsuite/gdb.arch/aarch64-fp.exp @@ -75,3 +75,28 @@ gdb_test "p/x \$fpcr" \ "fpcr.*0x\[0-9a-fA-F\].*" \ "check register fpcr value" +with_test_prefix "bfloat16" { + gdb_test "set \$h0.bf = 1.185e-38" \ + ".*" \ + "set h0.bf to 129" + + gdb_test "p \$h0" \ + "h0.*{bf = 1.185e-38, f = 7.689e-06, u = 129, s = 129}" \ + "h0 fields are valid" + + gdb_test "set \$v0.h.bf\[0\] = 0" \ + "v0.* = 0" \ + "set v0.h.bf\[0\] to 0" + + gdb_test "p \$v0.h.s\[0\]" \ + "v0.* = 0" \ + "v0.h.s\[0\] is 0" + + gdb_test "set \$v0.h.bf\[0\] = 1.185e-38" \ + "v0.* = 1.185e-38" \ + "set v0.h.bf\[0\] to 129" + + gdb_test "p \$v0.h.s\[0\]" \ + "v0.* = 129" \ + "v0.h.s\[0\] is 129" +} -- 2.30.2