From 52abf98184d47cc7d7a783cd9cba9c7a48e26894 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 24 Mar 2023 21:55:07 +0000 Subject: [PATCH] accidental removal of bold --- openpower/sv/rfc/ls001.mdwn | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index fd2c133ce..c772af807 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -1,4 +1,4 @@ -# OPF ISA WG External RFC LS001 v2 14Sep2022 +# OPF ISA WG External RFC LS001 v3 24mar2022 * RFC Author: Luke Kenneth Casson Leighton. * RFC Contributors/Ideas: Brad Frey, Paul Mackerras, Konstantinos Magritis, @@ -10,8 +10,8 @@ [[ls001/discussion]] This proposal is to extend the Power ISA with an Abstract RISC-Paradigm -Vectorisation Concept that may be orthogonally applied to **all and any** suitable -Scalar instructions, present and future, in the Scalar Power ISA. +Vectorisation Concept that may be orthogonally applied to **all and any** +suitable Scalar instructions, present and future, in the Scalar Power ISA. The Vectorisation System is called ["Simple-V"](https://libre-soc.org/openpower/sv/) and the Prefix Format is called @@ -33,7 +33,7 @@ Stakeholder, is to bring to market mass-volume general-purpose compute processors that are competitive in the 3D GPU Audio Visual DSP EDGE IoT desktop chromebook netbook smartphone laptop markets, performance-leveraged by Simple-V. To achieve this goal both Simple-V and accompanying -Scalar** Power ISA instructions are needed. These include IEEE754 +**Scalar** Power ISA instructions are needed. These include IEEE754 [Transcendentals](https://libre-soc.org/openpower/transcendentals/) [AV](https://libre-soc.org/openpower/sv/av_opcodes/) cryptographic -- 2.30.2